Electrical computers and digital processing systems: multicomput – Multiple network interconnecting
Patent
1996-12-30
2000-08-01
Matar, Ahmad F.
Electrical computers and digital processing systems: multicomput
Multiple network interconnecting
710 40, 370911, G06F 1516, G06F 300, H04L 1228
Patent
active
060981091
ABSTRACT:
A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value. The arbitration logic includes a receive arbiter and a transmit arbiter, each of which use a corresponding arbitration count.
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Hareski Patricia E.
Kotzur Gary B.
Mayer Dale J.
Walker William J.
Witkowski Michael L.
Caldwell Andrew
Compaq Computer Corporation
Matar Ahmad F.
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