Programmable antifuse structure, process, logic cell and archite

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3072021, 307469, 437922, 257530, H03K 19177

Patent

active

051665565

ABSTRACT:
An integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 500.degree. C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of the said antifuse layer in excess of 500.degree. C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti.sub.5 Si.sub.3, TiSi, and/or TiSi.sub.2 than is yielded TiO, Ti.sub.2 O.sub.3, Ti.sub.3 O.sub.5, and/or TiO.sub.2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.

REFERENCES:
patent: 4238839 (1980-12-01), Redfern et al.
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4420820 (1983-12-01), Preedy
patent: 4455495 (1984-06-01), Masuhara et al.
patent: 4507756 (1985-03-01), McElroy
patent: 4507757 (1985-03-01), McElroy
patent: 4565712 (1986-01-01), Naguchi et al.
patent: 4569120 (1986-02-01), Stacey et al.
patent: 4569121 (1986-02-01), Lim et al.
patent: 4585490 (1986-04-01), Raffel et al.
patent: 4590589 (1986-05-01), Gerzberg
patent: 4678889 (1987-07-01), Yamanaka
patent: 4721868 (1988-01-01), Cornell et al.
patent: 4748490 (1988-05-01), Hollingsworth
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4792835 (1988-12-01), Sacarisen et al.
patent: 4796074 (1989-01-01), Roesner
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4839864 (1989-06-01), Fujishima
patent: 4847732 (1989-07-01), Stopper et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4882611 (1989-11-01), Blech et al.
patent: 4893167 (1990-01-01), Boudou et al.
patent: 4897836 (1990-01-01), Fitzpatrick et al.
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 4910418 (1990-03-01), Graham et al.
patent: 4914055 (1990-03-01), Gordon et al.
patent: 4916809 (1990-04-01), Boudou et al.
patent: 4924287 (1990-05-01), Orbach
patent: 4937475 (1990-06-01), Rhodes et al.
patent: 5099149 (1992-03-01), Smith
Gullette et al, "Laser Personalization of NMOS Digital Topologies", 1983 IEEE Int'l Symposium on Circuits and Systems, Newport Beach, Calif. May 2-4, 1983, pp. 1249-1252.
Ron Iscoff, "Characterizing Quickturn ASICs: . . . ", Semiconductor International, Aug. 1990, pp. 68-73.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable antifuse structure, process, logic cell and archite does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable antifuse structure, process, logic cell and archite, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable antifuse structure, process, logic cell and archite will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-924208

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.