Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-11-03
2002-02-26
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C323S315000
Reexamination Certificate
active
06351177
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89111021, filed Jun. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a reference voltage generator. More particularly, the present invention relates to a programmable reference voltage generator capable producing a reference voltage relatively independent from any fluctuation in input voltage source.
2. Description of Related Art
Most devices inside an electronic module need a reference voltage to serve as source for driving, comparing or triggering whatever operations necessary. However, turning on an electronic module may produce a transient voltage surge and temperature may rise after running the module for awhile. All these factors may lead to some variation in the reference voltage. In other words, the reference voltage may fluctuate according to changes in the input voltage and may lead to system instability or circuit failure.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a programmable and input voltage independent reference voltage generator. The reference voltage generator comprises of a bandgap generation circuit, two amplifiers, two variable current sources, six PMOS transistors, five NMOS transistors and four resistors. The bandgap generation circuit provides an operating voltage. Both the negative terminal of the first amplifier and the positive terminal of the second amplifier receive the operating voltage from the bandgap generation circuit. The negative terminal of the second amplifier is connected to a first node point and the output terminal of the second amplifier is connected to a second node point. The source terminal of the first PMOS transistor is connected to a voltage source. The gate terminal of the first PMOS transistor is connected to the output terminal of the first amplifier. The drain terminal of the first PMOS transistor is connected to the positive input terminal of the first amplifier. The source terminal and the substrate of the second PMOS transistor are connected to a voltage source. The gate terminal of the second PMOS transistor is connected to the output terminal of the first amplifier. The source terminal and the substrate of the third PMOS transistor are connected to the voltage source. The gate terminal and the drain terminal of the third PMOS transistor are coupled to each other. The source terminal and the substrate of the fourth PMOS transistor are connected to the voltage source. The gate terminal of the fourth PMOS transistor is connected to the gate terminal of the third PMOS transistor. The source terminal and the substrate of the fifth PMOS transistor are connected to the voltage source. The gate terminal and the drain terminal of the fifth PMOS transistor are coupled to each other. The source terminal and the substrate of the sixth PMOS transistor are connected to the voltage source. The gate terminal of the sixth PMOS transistor is connected to the drain terminal of the fifth MOS transistor. The drain terminal of the sixth PMOS transistor is connected to a fourth node point.
The source terminal and the substrate of the first NMOS transistor are connected to a ground voltage. The gate terminal and the drain terminal of the first NMOS transistor are coupled to each other and connected to the drain terminal of the second PMOS transistor. The source terminal and the substrate of the second NMOS transistor are connected to the ground voltage. The gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor. The drain terminal of the second NMOS transistor is connected to the drain terminal of the third PMOS transistor. The source terminal and the substrate of the third NMOS transistor are connected to the ground voltage. The gate terminal and the drain terminal of the third NMOS transistor are connected to each other and to the drain terminal of the fourth PMOS transistor. The source terminal and the substrate of the fourth NMOS transistor are connected to the ground voltage. The gate terminal of the fourth NMOS transistor is connected to the gate terminal of the third NMOS transistor. The drain terminal of the fourth NMOS transistor is connected to the drain terminal of the fifth PMOS transistor. The source terminal and the substrate of the fifth NMOS transistor are connected to the ground voltage. The gate terminal of the fifth NMOS transistor is connected to the gate terminal of the fourth NMOS transistor. The drain terminal of the fifth NMOS transistor is connected to the third node point. The input terminal of the first variable current source is connected to the voltage source. The output terminal of the first variable current source is connected to the drain terminal of the fourth PMOS transistor. The input terminal of the second variable current source is connected to the voltage source. The output terminal of the second variable current source is connected to the fourth node point. The first resistor connects between the positive terminal of the first amplifier and ground. The second resistor connects between the first node point and the second node point. The third resistor connects between the first node point and the third node point. The fourth resistor connected between the fourth node pint and the ground. The first, second, third and fourth node point are used for outputting a first, second, third and fourth reference voltage respectively.
The programmable and input voltage independent reference voltage generator of this invention uses a current mirror and a plurality of MOS switches to control size of current so that size of the reference voltage can be adjusted. According to this invention, no decoding circuits are employed. By adjusting values of resistors and dimensional ratio between the current mirror and MOS, a relatively small circuit area (for example, smaller than a decoding circuit) is needed to house the voltage generator circuit. In addition, the invention is able to provide an adjustable but highly stable reference voltages to electronic modules such as A/D or D/A converters or clamping circuits. Hence, performance of application circuits can be optimized through the highly flexible generation method used by the reference voltage generator.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5825167 (1998-10-01), Ryat
Huang Chung-Chin
Lin Yue-Zen
Wang Chien-Kuo
J. C. Patents
Macronix International Co. Ltd.
Wells Kenneth B.
LandOfFree
Programmable and input voltage independent reference voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable and input voltage independent reference voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable and input voltage independent reference voltage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2973925