Programmable and convertible non-volatile memory array

Details Programmable and convertible non-volatile memory array Programmable and convertible non-volatile memory array

1996-07-19

1998-12-01

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518526, 36518529, 36518533, 365218, G11C 1134, G11C 700

Patent

active

058448390

ABSTRACT:
A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected. The decoder circuit also includes a high power pass device 82 associated with each row line, having one of its source and drain connected to the associated row node, having the other of its source and drain connected to a row line and having its gate connected to a first voltage, lower than the high voltage, so as to couple the signal on the row node to the row line. Finally, a keeper circuit 102 is provided, associated with each row line and coupled to the high voltage for sensing the signal on the row line and in response thereto for coupling the high voltage to the row line. The memory has high speed, since the decoder logic is performed by low power devices. In addition, in fabrication the memory is readily convertible to a permanent ROM by eliminating the formation of the floating gate, bypassing the high power pass device and not connecting the keeper circuit.

REFERENCES:
patent: 5359558 (1994-10-01), Chang et al.
patent: 5559742 (1996-09-01), Lee et al.

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