Programmable and convertible non-volatile memory array

Details Programmable and convertible non-volatile memory array Programmable and convertible non-volatile memory array

1996-07-19

1998-03-24

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518526, 365218, 257315, 257316, 257544, G11C 700

Patent

active

057320217

ABSTRACT:
A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines. The method is particularly suited to Flash memories. Erasure can be sectored by grouping cells in separate ones of the first wells and applying the method selectably to such groups.

REFERENCES:
patent: 4435790 (1984-03-01), Tickle et al.
patent: 4958317 (1990-09-01), Terada et al.
patent: 5515319 (1996-05-01), Smayling et al.

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