Programmable analog-to-digital converter with bit conversion...

Details Programmable analog-to-digital converter with bit conversion... Programmable analog-to-digital converter with bit conversion...

2000-06-15

2001-12-11

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S165000

Reexamination Certificate

active

06329938

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to rotating magnetic storage devices, and more particularly to analog to digital conversion of signals related to those storage devices.
2. Description of the Related Art
Analog-to-digital converters (ADC) are widely used in digital devices to interface between the analog and digital world. An ADC converts an analog signal such as a voltage or a current into a digital signal that can be further processed, stored, and decimated using digital computers. For example, ADCs are used in communications, appliances, signal processing, computers, and any other fields that require conversion of analog signals into digital forms.
As is well known in the art, the ADC encodes an analog input signal into a digital output signal of a predetermined bit length, N. The encoding of the analog input V
A
, into a digital output signal of N-bits is typically approximated as a binary fraction of a full-scale output voltage, V
SS
. Hence, the output of the converter corresponds to an N-bit digital word D given as:
D=V
A
/V
SS
=(
B
1
/2
1
)+(
B
2
/2
2
)+ . . . +(
B
N
/2
N
),
where B
1
, B
2
, . . . , B
N
are the binary bit coefficients having a value of either a one or a zero. In this setting, the binary coefficient B1 represents the most significant bit while B
N
represents the least significant bit of the digital word. The binary bit coefficients are obtained from the output of the ADC converter.
Conventional ADCs often use a successive approximation of techniques to convert an analog signal into a digital signal. In successive approximation methods, the analog input voltage is successively approximated one bit at a time to arrive at the output digital voltage signal. For example, for a 10-bit result, ten different approximations take place with one approximation to set each one of the bits.
Typically, conventional ADCs use a fixed number of clock cycles for all of the bits to be set so that the same amount of time is used for each bit approximation. In practice, however, the number of clock cycles needed to set each of the bits is usually different for each of the bits. These ADCs select a period of time for clock cycle based on the worst bit case in the approximation. For example, the most significant bit may require 16 clock cycles to convert. For all subsequent bits, the clock cycles for this worst case bit is used to set each of the bits even though the remaining bits may not require as many clock cycles to convert. This means that for the rest of the bits, substantial amount of time will be wasted. Accordingly, the speed of the ADC in converting an analog signal to a digital data may consume significantly more time than is necessary.
Thus, what is needed is an ADC that can convert individual data bits in clock cycles that are tailored to the timing requirements for each individual data bits to reduce conversion time. What is also needed is an ADC converter that is programmable to the conversion time requirements of different ADC converters bits due to manufacturing process variations.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing programmable ADC with bit conversion optimization and method therefor. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a programmable ADC with bit conversion optimization. The programmable ADC includes an amplifier, a programmable clock generator, a comparator, a successive approximation logic, a digital-to-analog converter, and a voltage converter. The amplifier is arranged to sample and hold an input analog signal to be converted into N digital data bits. The programmable clock generator generates a clock signal for each of the N-bits to trigger setting of one of the N-bit digital data bits such that each of the N bits is set during a time optimized for each bit. The comparator is coupled to receive and compare the input analog signal with a successively approximated analog signal to generate a digital output signal. The successive approximation logic is configured to successively set each of the N-bits in response to the digital output signal and the clock signal to generate a successively approximated N-bit digital data. The digital-to-analog converter converts the successively approximated N-bit digital data into a successively approximated analog current signal. The voltage converter has a resistance value for converting the successively approximated analog current signals into the successively approximated analog voltage signal for input to the comparator. The voltage converter is arranged to optimize a time constant defined by the resistance and an output capacitance of the digital-to-analog converter. Preferably, the voltage converter is a variable or programmable resistor that can be set to a specified resistance value to speed up the digital-to-analog converter.
In another embodiment, the present invention provides a method for converting an analog voltage signal into digital data bits with bit conversion optimization. The method includes: (a) successively generating clock signals for a set of digital data bits, each clock signal being adapted to trigger setting of one of the digital data bits such that each of the bits is set during a time optimized for the bit; (b) comparing an input analog signal and a successively approximated analog voltage signal to generate a digital output signal; (c) successively setting each of the digital data bits in response to the digital output signal and the clock signal to generate a successively approximated digital data bits; (d) converting the successively approximated digital data bits into a successively approximated analog current signal; and (e) converting, by a resistor having a resistance value, the successively approximated analog current signal into the successively approximated analog voltage signal, the resistor being configured to optimize a time constant defined by the resistance and an output capacitance of the digital-to-analog converter.
Advantageously, the present invention thus optimizes conversion time for each individual bits by storing an optimum number of clock cycles for converting each individual bit. By setting each individual data bits one at a time by cycling through the stored optimum clock cycle numbers, the present invention substantially increases the speed of the ADC. In addition, a voltage converter such as a resistor is used to provide optimum time constant RC to further speed up the ADC to generate output digital data bits. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 4851838 (1989-07-01), Shier
patent: 5870052 (1999-02-01), Dedic et al.
patent: 6028545 (2000-02-01), Chen
Anonymous, “2.7 V to 5.5 V, 4.5 &mgr;s, 8-Bit ADC in 8-Lead microSOIC/DIP”, Analog Devices, AD7823, ©Analog Devices, Inc., 1998.
Grebene, “Bipolar and MOS Analog Integrated Circuit Design”, pp. 825-879, ©1984, John Wiley & Sons, Inc., Canada.

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