Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-07-01
2000-07-18
Phan, Trong
Static information storage and retrieval
Floating gate
Multiple values
36518533, G11C 1604
Patent
active
060916311
ABSTRACT:
A program/verify method for a multi-level flash memory array, wherein threshold values to be programmed into each flash memory cell are represented using binary bits. In the program/verify method for each cell, the most significant bit representing the threshold level to be programmed into a cell is read first and the cell is programmed to the minimum threshold level represented by the most significant bit. The next most significant bit is then read and if necessary further programming pulses are applied to complete programming. By programming to the level of the most significant bit first rather than programming to each possible threshold separately as determined by all bits read together, less time is required for programming an array.
REFERENCES:
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5694357 (1997-12-01), Mori
patent: 5768188 (1998-06-01), Park et al.
patent: 5815436 (1998-09-01), Tanaka et al.
patent: 5870218 (1999-02-01), Jyouno et al.
patent: 5894436 (1999-04-01), Ohkawa et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 5943260 (1999-08-01), Hirakawa
Kucera Joe
Skrovan Joseph
Advanced Micro Devices , Inc.
Phan Trong
LandOfFree
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