Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-02-05
1996-11-26
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
36518901, G11C 1300
Patent
active
055792626
ABSTRACT:
A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i.e., highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i.e., lowest) read voltage on the word lines of erased memory cells. So that there worst case voltages are stable and reproducible, they are generated using a feedback control circuit consisting of a comparator driven by a bandgap voltage reference (+1.28 VDC ), various feedback transistors and a voltage divider network. The worst case program verification voltage (+6.4 VDC) and the worst case erase verification voltage (+4.0 VDC) are selectively generated by the disclosed circuitry in response to program verify (PV) and erase verify (EV) signals generated by the host computer in which the memory system is installed. The host issues these signals, which initiate a verification operation, following each erase or program operation. If based on the cells' responses when stimulated by the worst case verification voltages it turns out that a program or erase operation was ineffective, the host repeats the memory operation until it is verified to be effective.
REFERENCES:
patent: 4875188 (1989-10-01), Jungroth
patent: 5365484 (1994-11-01), Cleveland et al.
Fears Terrell W.
Integrated Silicon Solution Inc.
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