Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
2001-08-06
2004-11-30
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S011000, C712S033000
Reexamination Certificate
active
06826674
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a control program product described with microcodes or the like, and a data processing system capable of executing the control program.
BACKGROUND OF THE INVENTION
Processors (data processing systems or LSIs) incorporating an operation function such as microprocessor (MPU) and digital signal processor (DSP) are known as apparatuses for conducting general-purpose processing and special digital data processing. Architectural factors that have significantly contributed to improved performance of these processors include pipelining technology, super-pipelining technology, super-scalar technology, VLIW technology, and addition of specialized data paths (special purpose instructions). The architectural elements further include branch prediction, register bank, cache technology, and the like.
In the VLIW technology, the data paths are configured in advance so as to allow for parallel execution, optimization is conducted so that a compiler improves the parallel execution and generates a proper VLIW instruction code. This technology adopts an extremely rational idea, eliminating the need for the circuitry for checking the likelihood of parallel execution of individual instructions as in the super-scalar. Therefore, this technology is considered to be extremely promising as means for realizing the hardware for parallel execution. However, given a processor for use in processing of an application that requires image processing or special data processing, the VLIW is not an optimal solution either. This is because, particularly in applications requiring continuous or sequential processing using the operation results, there is a limit in executing operations or data processing while holding the data in a general-purpose register as in VLIW. This problem is the same in the conventional pipeline technology.
On the other hand, it is well known from the past experiences that various matrix calculations, vector calculations and the like are conducted with higher performance when implemented in dedicated circuitry. Therefore, in the most advanced technology for achieving the highest performance, the idea based on the VLIW becomes major with the various dedicated arithmetic circuits mounted according to the purpose of applications.
However, the VLIW is the technology of improving the parallel-processing execution efficiency near a program counter. Therefore, the VLIW is not so effective in, e.g., executing two or more objects simultaneously or executing two or more functions. Moreover, mounting various dedicated arithmetic circuits increases the hardware, also reduces software flexibility.
The architecture of FPGA (Field Programmable Gate Arrays) is capable of changing connection between transistors and controlling dynamically to some degree, therefore, various dedicated arithmetic circuits may be implemented. However, in FPGA based architecture, it takes a long time for dynamically changing the hardware, and some another hardware for reducing that time is required. Therefore, it is difficult to dynamically control the hardware during execution of the application actually, and it dose not become an economical solution. It is possible to retain the reconfiguration information of the FPGA in a RAM of two faces or more for operating in the background so as to dynamically change the architecture in an apparently short time. However, in order to enable this reconfiguration to be conducted within several clocks, it is required to mount the RAM that stores all of number of combinations of information for reconfiguring the FPGA. This does not at all essentially solve the economical problem of a long reconfiguration time of the FPGA. Moreover, the original problem of the FPGA, i.e. poor AC characteristics at the practical level, that comes from the purpose of FPGA to efficiently implementing mapping in terms of the gate of the hardware, is not likely to be solved for the time being.
It is therefore an object of the present invention to provide a system, such as a program product, a data processing system capable of executing the program and a control method of the processing system, in the system, complicated data processings are flexibly executed at a high speed without using various dedicated circuits specific to those data processings originally. It is another object of the present invention to provide a more economical data processing system, a control method of the processing system and a program product, allowing for dynamic hardware control even during execution of an application, and capable of implementing the software-level flexibility at the hardware level and of executing various data processings at a high speed.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a program product for controlling a data processing system including a plurality of processing units. The program product or program apparatus including a data flow designation instruction for designating input and/or output interfaces of at least one of the processing units independently of the time or timing of execution of the processing unit so as to define a data path configured by the processing unit. This program can be provided in a form recorded or stored on a recording medium readable with the data processing system, such as ROM or RAM. This program can alternatively be provided in a form embedded in a transmission medium capable of being transmitted over a computer network or another communication.
The present invention also provides the data processing system comprising a plurality of processing units including changeable input and/or output interfaces; a unit for fetching the data flow designation instruction for designating the input and/or output intercedes of at least one of the processing units independently of the time or timing of execution of the processing unit; and a data flow designation unit for decoding the data flow designation instruction and setting the input and/or output interfaces of the processing unit so as to configure a data path from a plurality of the processing units. The program product of the present invention controls the processing system. Accordingly, the data path formed from a combination of a plurality of processing units is changed with the program, so that various data processings are executed with hardware, i.e., the data path or data flow, that is suitable for each of that various processings.
A method for controlling the data processing system according to the present invention includes a step of fetching a data flow designation instruction that designates the input and/or output interfaces of at least one of the processing units independent of the processing execution timing of the processing unit; and a data flow designation step of decoding the data flow designation instruction and setting the input and/or output interfaces of the processing unit so as to configure some data path from a plurality of the processing units.
Conventionally, the only way to handle with a complicated data processing is to prepare dedicated circuitry and implement a special instruction for using the circuitry, thereby increasing the hardware costs. In contrast, in the system of the present invention, such as the program product, data processing system and control method thereof, the interfaces of the processing unit as an arithmetic logic unit are described, making it possible to introduce the structure of pipeline control and data path control into an instruction set, i.e., program product. This allows various data processings to be described with the program and executed with suitable hardware, whereby the data processing system having both the software flexibility and high-speed performance using dedicated circuitry is provided by this invention. Moreover, these data paths can be implemented without discontinuing execution of a main processing or general-purpose processing, therefore, the hardware is dynamic reconfigured during execution of an application.
Moreover, the present invention provides means that is effective not only in execu
IP Flex Inc.
Treat William M.
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