Program execution control device having addressability in accord

Details Program execution control device having addressability in accord Program execution control device having addressability in accord

1995-06-05

1997-07-22

Lim, Krisna

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Histogram processing

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395381, 382160, 371 224, 36471701, 365240, G06F 930

Patent

active

056511230

ABSTRACT:
Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

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Tietze, Ulrich; Schenk, Christoph, "Halbleiterschaltungs-technik, 5th edit., Springer-Verlag", 1980, ISBN 3-540-09848-8, pp. 509-512.

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