Program/erase method for P-channel charge trapping memory...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185290

Reexamination Certificate

active

07133316

ABSTRACT:
A method of operating a memory device is disclosed, wherein the memory device includes an n-type substrate and a plurality of memory cells formed thereon, each memory cell corresponding to a word line, a first bit line, and second bit line, and including a first bit portion and a second bit portion each for storing one bit of information. The method includes resetting a selected memory cell by applying a first negative bias to the word line of the selected memory cell and applying a ground bias to the first and second bit lines, and programming the first bit portion of the selected memory cell by applying a first positive bias to the word line of the selected memory cell, applying a second negative bias to the first bit line of the selected memory cell, and applying a ground bias to the second bit line of the selected memory cell.

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C.C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEDM 2002, pp. 931-934.
T. Ohnakado et al., “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell,” IEDM, 1995, Section 11.5, pp. 279-282.
Marvin H. White et al., “On the go with SONOS,” IEEE Circuit and Device Magazine, Jul. 2000, pp. 22-31.

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