Program/erase endurance of EEPROM memory cells

Details Program/erase endurance of EEPROM memory cells Program/erase endurance of EEPROM memory cells

1999-02-04

2000-12-05

Elms, Richard

Static information storage and retrieval

Floating gate

Particular biasing

36518503, 36518529, G11C 1604

Patent

active

061575704

ABSTRACT:
A circuit and method increases the endurance of memory cells in a memory array by decreasing the number of times a memory cell is programmed or erased. A bit-wise program/erase controller coupled to the memory array modifies the erasing and programming of multi-bit data words by erasing only those memory cells which must be erased and programming only those memory cells which must be programmed. Specifically, the bit-wise program/erase controller compares a new data word, which will be written into the memory array at a write address, with the current data word at the write address. The memory cells at the write address are categorized into a first subset and a second subset. The first subset of memory cells are currently in a programmed state but must be erased because the corresponding bit of the new data word is at an erased logic level. The second subset of memory cells are currently in an erased state but must be programmed because the corresponding bit of the new data word is at a programmed logic level. Bit-wise program/erase controller erases only the first subset of memory cells and programs only the second subset of memory cells. Thus, over multiple writes into the memory array, the number times each memory cell is erased or programmed is reduced resulting in greater endurance of the memory cells.

REFERENCES:
patent: 5412601 (1995-05-01), Sawada et al.
patent: 5434825 (1995-07-01), Harari
patent: 5768192 (1998-06-01), Eitan
patent: 5966332 (1999-10-01), Takano
patent: 6001725 (2000-01-01), Eitan

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