Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-02-02
1996-10-22
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
365218, G11C 1300
Patent
active
055684254
ABSTRACT:
A program drain voltage control system is disclosed for use within an EPROM/flash memory system wherein each memory cell is coupled in series with plural y selection transistors. When the EPROM/flash memory system is in programming mode, the control system maintains the program drain voltage of EPROM/flash memory cells being programmed at a target drain voltage (+6.1 VDC ). Drain voltage control is accomplished using a current control circuit and a voltage control circuit. The voltage control circuit uses a comparator driven by a voltage reference signal (+1.28 VDC) derived from the bandgap reference and by a voltage divider output. When the output from the voltage divider is larger than the reference voltage, the comparator output goes high, turning on a pulldown transistor, which pulls down the node where the target voltage is to be established. So that the target drain voltage is correctly mirrored at the drain of the memory cells being programmed, the target drain voltage is coupled to the drain of a first of the y selector transistor through a like number of identical pass transistors. The current control circuit uses a n-channel native transistor whose gate is coupled to the same voltage reference (1.28 VDC) to generate a known drain voltage for a second EPROM/flash memory cell. This causes the second memory cell to draw a known current that is multiplied and then mirrored into the voltage control circuit so that the target drain voltage is achieved at currents that approximate actual memory cell programming currents.
REFERENCES:
patent: 5140553 (1992-08-01), Choi et al.
Fears Terrell W.
Integrated Silicon Solution Inc.
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