Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2011-03-22
2011-03-22
Kundu, Sujoy K (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S033000, C702S034000, C702S057000, C702S081000, C702S082000, C702S083000, C702S084000, C702S118000, C702S120000, C702S123000, C702S124000, C702S125000, C702S182000, C702S183000, C714S030000, C714S032000, C714S039000, C714S724000, C714S727000, C714S732000, C714S733000, C714S738000, C714S745000
Reexamination Certificate
active
07912669
ABSTRACT:
A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.
REFERENCES:
patent: 6370492 (2002-04-01), Akin
patent: 6378094 (2002-04-01), Chakraborty et al.
patent: 6421618 (2002-07-01), Kliman et al.
patent: 2004/0168108 (2004-08-01), Chan et al.
patent: 2006/0010352 (2006-01-01), Mukherjee et al.
patent: 2007/0038911 (2007-02-01), Koenemann et al.
Bushnell et al.,“Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits,” 2001, Library of Congress Cataloging-in-Publication Data, p. 64, 385-412.
He et al., “A Neural Network Approach for fault Diagnosis of Large-scale Analogue Circuits,” Circuit and Systems 2002, ISCAS 2002, IEEE International Symposium, vol. 1, p. I-153-I-156.
Bandler et al., “Fault diagnosis of analog circuits,” Proceedings of the IEEE, vol. 73, Issue 8, Aug. 1985, p. 1279-1352.
Bushnell et al.,“Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits,” 2001, Library of Congress Cataloging-in-Publication Data, p. 64, 598-604.
Ramakrishnan, A. , et al., “A life consumption monitoring methodology for electronic systems”,IEEE Transactions on Components and Packaging Technologies, [see also Components, Packaging and Manufacturing Technology, Part A: Packaging Technologies, IEEE Transactions on],26(3), (Sep. 2003),625-634.
Vichare, N. , et al., “Health and Life Consumption Monitoring of Electronic Products”, http://www.calce.umd.edu/whats—new/upcoming/2004/workshop/06.pdf, CALCE Team—University of Maryland,(2004),1-35.
Honeywell International , Inc.
Kundu Sujoy K
Schwegman Lundberg & Woessner, P.A.
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