Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1999-02-08
2003-06-17
Jones, Hugh M. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S002000, C703S014000, C438S142000, C438S199000, C438S289000
Reexamination Certificate
active
06581028
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a profile extraction method and a profile extraction apparatus.
In recent years, as further miniaturization of MOSFET devices has been achieved through advances in integration technology such as LSI, it has become difficult to directly detect the impurity concentration distribution (hereafter referred to as “profile”) from a device at the actual product level (hereafter referred to as “actual device”). Since various characteristics are affected by the profile in a MOSFET, it is crucial that accurate profile extraction be achieved in order to realize a higher degree of efficiency in production. Such circumstances have rendered even more importance to the inverse modeling technology, i.e., the technology through which the profile is extracted through simulation implemented by utilizing the electrical characteristics measured from the device.
The profile extraction methods in the prior art that employ the inverse modeling technology include, for instance, the method disclosed in K. Khalil et al., IEEE EDL-16 (1), p.17, 1995. In the profile extraction method disclosed in this publication, the capacity-voltage characteristics (hereafter referred to as “C-V characteristics”) of various TEG patterns and sample devices are utilized as the electrical characteristics. In this context, “TEG” stands for “test element group”, which means a test piece group. In addition, a sample device refers to a device exclusively used for testing, which is prepared at a size that allows measurement through processes similar to those for manufacturing an actual device.
The method disclosed in Z. K. Lee et al., IEDM Tech. Dig. pp. 683, 1997 is another example of a profile extraction method adopting the inverse modeling technology. In the profile extraction method disclosed in this publication, the currentvoltage characteristics (hereafter referred to as “I-V characteristics”) of one device only are utilized as the electrical characteristics, and the channel profile is extracted with the source/drain profile (hereafter referred to as “S/D profile”) remaining fixed. In this context, the S/D profile refers to impurity concentration distribution in the source area/drain area, and the channel profile refers to the impurity concentration distribution in the substrate area formed under the gate electrodes.
However, the profile extraction methods in the prior art described above require a special TEG pattern or a large sample device to obtain measured values representing the electrical characteristics, and moreover, there is a possibility that the extracted profile which is the profile of a sample device or the like may be different from the profile of the actual device.
In addition, when a two-dimensional channel profile with the direction of the length of the channel assuming one dimension and the direction of the depth of the channel assuming the other dimension is extracted with the S/D profile fixed, the extracted two-dimensional channel profile may not be utilized for other MOSFETs having different S/D profiles. Furthermore, since the two-dimensional channel profile is determined based upon the electrical characteristics of one device in the prior art, there is a possibility that the extracted two-dimensional channel profile cannot assure the electrical characteristics of another device with different design requirements such as, for instance, a different gate length. It is to be noted that the gate length refers to the distance from the drain end to the source end.
Moreover, since the sensitivity of the two-dimensional channel profile with respect to the electrical characteristics decreases as the gate length is increased in a MOSFET, accurate profile extraction is difficult in the profile extraction methods in the prior art. Also, since it is necessary to perform individual calculations for each device in the profile extraction methods in the prior art, the length of time required for calculation increases as the number of devices for extraction increases.
SUMMARY OF THE INVENTION
An object of the present invention, which has been completed by addressing the problems of the profile extraction methods in the prior art discussed above, is to provide a new and improved profile extraction method and a new and improved profile extraction apparatus that make it possible to extract a profile from an actual semiconductor device.
Another object of the present invention is to provide a new and improved profile extraction method and a new and improved profile extraction apparatus through which, an S/D profile as well as a channel profile can be extracted.
Yet another object of the present invention is to provide a new and improved profile extraction method and a new and improved profile extraction apparatus that are capable of achieving extraction results which assure profiles of a plurality of semiconductor devices having different gate lengths.
Yet another object of the present invention is to provide a new and improved profile extraction method and a new and improved profile extraction apparatus in which calculation is simpler and is executed faster.
Normally, in a semiconductor device such as a MOSFET, the source area and the drain area, which have higher impurity concentrations than the substrate area under the gate electrodes, are highly conductive. Consequently, the effect of the S/D profile on the electrical characteristics is not taken into consideration when performing profile extraction in the prior art. However, channel profiles in the vicinity of the source end and in the vicinity of the drain end are subject to the effect of the S/D profile due to factors such as impurity ion implantation implemented during the formation of the source area and the drain area. When the channel profile is under the influence of the S/D profile in this manner, while the electrical characteristics in a semiconductor device having a large gate length are only affected to a small enough degree to be disregarded, the electrical characteristics in a semiconductor device having a small gate length are affected to a significant degree that cannot be disregarded.
The inventor of the present invention has learned that the reverse short channel effect, which is known only through experience, can be explained by incorporating the above observation. The reverse short channel effect in this context refers to a phenomenon in which the threshold voltage temporarily rises before the short channel effect becomes pronounced. It is to be noted that the short channel effect refers to a phenomenon in which the threshold voltage falls drastically as the gate length is reduced in a semiconductor device such as a MOSFET. It is known in the prior art that the short channel effect is caused by the depletion layer extending from the drain area and the depletion layer extending from the source area projecting out to the substrate area under the gate electrodes. However, the cause of the reverse short channel effect has not yet been clarified.
FIG. 5
presents the results of measurement of the characteristics of the threshold voltage Vth relative to the gate length Lg (hereafter referred to as the “Vth-Lg characteristics”) in a MOSFET with the substrate bias voltage Vsub set at 0, −3 and −5. In
FIG. 5
, a parameter k that indicates the shape of the drain end is incorporated, with the dotted line representing the results of measurement performed when k=1.0 and the solid line representing the results of measurement performed when k=2.0. As
FIG. 5
illustrates, the Vsub dependency of the Vth-Lg characteristics is sensitive to change in the shape of the S/D profile when the substrate bias voltage Vsub is not 0 (Vsub =−3, −5).
The above observation leads to the conclusion that the effect of the S/D profile must be fully considered in order to accurately extract the channel profile of a semiconductor device.
Accordingly, in order to achieve the objects described above, the profile extraction method for extracting a profile of a semiconductor device
Jones Hugh M.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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