Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
1998-12-01
2001-04-03
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C703S017000, C714S033000, C714S739000
Reexamination Certificate
active
06212493
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the design of microprocessors and similarly complicated integrated circuit devices and in particular to the development of functional test programs.
BACKGROUND OF THE INVENTION
Because of the rapid growth in the complexity of microprocessors, various methods have been developed for expediting the verification of a design prior to its actual implementation in hardware. Most of these methods relate to functional testing which uses information concerning desired behaviors specified by the designer of the microprocessor during a design phase. For example, these methods typically evolve around functional tests which use the instruction set of the microprocessor. Such functional testing has been generally proven to be reliable and robust.
In the typical scenario, a hardware design language is used to develop a register and logic gate level description of the processor in software. The functional test programs can then be written in any convenient computer language such as C++. The functional test is then run on the hardware description language model of the processor. The relative effectiveness of functional test programs depends upon how quickly the functional test can be completed, how well the functional model can be examined for errors, and the time required to generate the test software.
In general, two different techniques have evolved for developing functional test programs, including random generation and manual generation. The oldest method for developing functional test programs is write them manually. Typically, the functional test is implemented as a specialized program written by one of the hardware designers. While these types of programs are typically more expensive to develop and consume much programming time, they are often more effective than randomly developed sequences, since they can be written to target a particular feature of the microprocessor.
The known methods for manually generating test programs have a number of problems. For example, functional models that are tested using manually written programs may contain errors that the designers of the programs did not contemplate. The time that it takes to write a functional level test by hand versus the limited number of tests and limited variety of test sequences also makes manual testing a long and involved process.
Methods that use random instruction generators are considered to be inexpensive and efficient in many applications, and experience has been that they optimize the cost and speed at which errors can be found. With this technique, instruction sequences are produced by generating random binary patterns and then automatically translating them into an instruction sequence.
Unfortunately, randomly generated tests are not necessarily well adapted for determining whether a design will correctly execute all types of instruction sequences. For example, certain functions which are desirable to test may involve a particular sequence of internal instructions and external events. However, such external events are ordinally not synchronized with clock signals that determine the internal events.
Consider, for example, an external probe command of the type which is provided by another processor which is external to the microprocessor being tested but which contains a request for access to shared resource such as memory locations. Such probe commands usually have an address associated with them whereby the external processor is attempting to gain access to a shared memory location which is already being cached by the processor.
It is quite possible for an error in the hardware design for implementing a probe command to cause the microprocessor to produce an incorrect result when certain sequences of these activities occur. For example, the state of the cache memory of the processor under test and other registers may be critical as to whether the probe command is correctly handled. In order to devise an effective test for such an activity, access to the internal state of the processor is therefore typically required.
The problem with using randomly generated test programs is that they are not as effective in testing for known combinations of internal and external events. Ideally, in order to test microprocessor logic, the data or address associated with the test probe command relates in some way to data or an address which is already in use by the microprocessor or otherwise derived in some way from its present state.
Synchronization problems also develop with such an approach, since it takes a while typically for a probe command to reach over the system bus and arrive at the processor under test.
SUMMARY OF THE INVENTION
If one could predict which addresses or data would be in use at the time that a processor determines that it will accept a probe command, such functional tests would be more effective.
It would also be desirable for a functional test to verify external probe commands, interrupts, and similar instructions using random instruction generation techniques in a way that they are more effective.
A more effective randomized testing scheme could be implemented by anticipating internal events and initiating external events, thereby directly causing desirable interactions to occur.
More particularly, random stimulus could be used to create internal events within the microprocessor design simulation, while also applying external events which in turn interact with the internal events. These interactions would produce meaningful test cases when they result in conflicts with one another.
Unlike previous verification methods that typically generate external events randomly, both the type of event and its time of occurrence could be decided depending upon the current internal state, to increase the likelihood of generating conflicting external interactions.
The present invention is therefore a method and/or apparatus for generating functional test programs which include randomly generated instruction sequences. Initial profile information is recorded from a running randomly generated test instruction sequence which includes information such as instruction types, addresses and other statistics. In a second pass, the profile information is used to change the random test program in some way or to change the behavior of external events, so that contentions between events of interest are more likely to occur.
More particularly, a software simulation of the processor is first developed such as in a hardware description language. Next, a functional test program is developed, preferably by generating a random binary pattern and then translating it into an instruction sequence. In a first pass, the instruction sequence is then run on the hardware simulator. During this first pass, statistics relating to the state of the processor during the running of the random program are collected. For example, information concerning the memory addresses accesses by the program, the states of the program counter, instruction types, and other information is collected in a profile data file.
In a second pass, information from the stored profile from the first run of the program is used to generate directed simulation events. For example, a probe command using one of the addresses from the profile data file may be sent to the processor as a directed simulation event.
Another aspect of the invention takes into account the fact that many modern microprocessors use cache memories and out of order instruction execution. In other words, instructions may sometimes be speculatively issued from an instruction queue prior to actually completing the instruction. Furthermore, cache memories operating in accordance with a pyramidal hierarchal structure may contain multiple copies of the same data.
To provide some type of synchronization of the running random program with the external events, rather than simply recording an instruction cycle number or other time index in the profile data file, program counter information is also stored with the profile data. Using this information, a test
Asher David H.
Huggins James D.
Keller James B.
Choi Kyle J.
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
Teska Kevin J.
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