Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2001-11-28
2003-06-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S706000, C438S753000, C438S906000
Reexamination Certificate
active
06583029
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for manufacturing a silicon wafer and a bonded wafer such as a bounded SOI (silicon on insulator) wafer and a direct bond wafer. More specifically, the present invention relates to a silicon wafer which reduces polishing sag generated in the peripheral portion of the wafer, a bonded SOI wafer and a direct bond wafer which have no periphery removing region or reduce it, and a manufacturing method thereof.
BACKGROUND ART
A typical process for manufacturing a silicon mirror wafer is known to have a slice step for slicing a silicon single crystal ingot in a wafer shape using a wire saw or an inner diameter slicer, a chamfering step for chamfering the peripheral portion of the wafer for preventing cracks or fractures of the sliced wafer, a lapping step for lapping the wafer using loose abrasives to enhance flatness, an etching step for etching the wafer using an acid solution or an alkaline solution to remove processing deformation, and a mirror polishing step for polishing at least one of the surfaces thereof.
In the mirror polishing step, since a hard silicon wafer is mirror finished with a soft polishing cloth by mechanochemical polishing, a region called polishing sag (hereinafter, also called peripheral sag) as shown in
FIG. 5
exists in the peripheral portion thereof. The polishing sag which affects device fabrication is desirably eliminated to a minimum. Only mechanical polishing must be performed in order to thoroughly remove polishing sag. Even when using a processing method in a ductile mode which is a method for preventing crack damage by machining, the processing generates dislocation which must be removed by mechanochemical polishing. As a result, the polishing sag cannot be avoided.
Such a silicon mirror wafer is used to manufacture a bonded SOI wafer. The bonded SOI wafer is a technique for bonding two silicon wafers together via a silicon oxide film. As disclosed in Japanese Patent Publication No. Hei 5-46086, there has been known a method in which an oxide film is formed on at least one of the two wafers, the wafers are closely contacted with each other so as not to contain any foreign matters between the surfaces to be bonded, and they are subjected to a heat treatment at a temperature of 200 to 1200° C. to enhance the bonding strength.
The bonded wafer whose bonding strength is enhanced by performing a heat treatment can be subjected to later grinding and polishing processes. The thickness of the device fabrication side wafer is reduced to a desired thickness by grinding and polishing to form an SOI layer for device forming.
Since both the wafer surfaces before being bonded are mirror finished by mechanochemical polishing as described above, polishing sag exists in the peripheral portion thereof. An unbonded region of, e.g., about 1 to 3 mm is generated in the peripheral portion of the bonded wafer manufactured by bonding both the wafers together.
When one of the wafers is ground and polished while the unbonded region remains, the unbonded region is separated in the process, so that damage or particle attachment adversely will affect the device forming region. The unbonded region must be removed previously.
Japanese Laid-Open Patent Publication No. Hei 6-176993 proposes a method for manufacturing a bonded wafer in which two silicon wafers are closely contacted with each other via an oxide film, a region including an unbonded region of the periphery of a bonded wafer whose bonding strength is enhanced by subjecting the silicon wafers to a heat treatment in an oxidizing atmosphere is ground from the front surface side of the bond wafer (a first silicon wafer as a device region) in the thickness direction to a portion immediately before a bonding interface between the bond wafer and the base wafer (a second silicon wafer as a support), the bond wafer is etched to the bonding interface so as to thoroughly remove the unbonded region, and the bond wafer is ground and polished to reduce its thickness to a desired thickness.
According to this method, the unbonded region can be removed without changing the shape of the base wafer. As a periphery removing width for thoroughly removing the unbonded region, a portion of at least 3 mm from the peripheral edge of the bond wafer is typically removed in view of safety.
Also is known a technique for reducing an unbonded region (Japanese Laid-Open Patent Publication No. Hei 11-26336) in which a joined wafer is subjected to a heat treatment in an oxidizing atmosphere so as to fill an unbonded region of the periphery thereof with a thermal oxide film. A thermal oxidation treatment must be performed at high temperatures for a long time in order to sufficiently fill the unbonded region with the thermal oxide film, and enough bonding strength cannot be obtained. As a further method, Japanese Patent Publication No. Hei 4-4742 describes a technique for removing an unbonded region in which two wafers are bonded together, and the peripheral portions of both the wafers are ground at the same time to reduce the diameter of the wafers.
This method can obtain an SOI wafer having no periphery removing region in an SOI layer, as disclosed in the Japanese Laid-Open Patent Publication No. Hei 6-176993. A wafer having a diameter larger than the standard diameter of an SOI wafer to be manufactured must be used as a raw material wafer.
In addition, there has been known a method for manufacturing a direct bond wafer in which silicon wafers are directly contacted with each other without interposing an oxide film, and they are subjected to a heat treatment to enhance the bonding strength. There is the same problem as that of the bonded SOI wafer with respect to the unbonded region of the peripheral portion of a thickness-reduced layer (bond layer).
In recent years, with high-integration and high-speed of semiconductor devices, the thickness of the SOI layer must be made smaller and improve the film thickness uniformity. Specifically, the film thickness and the film thickness uniformity of about 0.1±0.01 &mgr;m are required.
In order that the thin film SOI wafer having such a film thickness and film thickness uniformity is realized by a bonded wafer, the prior art process for reducing the thickness using grinding and polishing cannot be employed. As a new thin-film technique, there is developed a method called an ion implantation separation method (also called a Smart Cut (trademark) method) disclosed in Japanese Laid-Open Patent Publication No. Hei 5-211128.
This ion implantation separation method is a technique that comprises forming an oxide film on at least one of two silicon wafers, implanting at least one of hydrogen ions or rare gas ions into one of the silicon wafers (hereinafter, also called a bond wafer) from its upper surface to form a fine bubble layer (enclosed layer) inside the silicon wafer, bringing the ion-implanted surface into contact with the other wafer (hereinafter, also called a base wafer) via the oxide film, then subjecting the wafers to a heat treatment (separation heat treatment) to separate one of the wafer as a thin-film at the fine bubble layer as a cleavage plane (separating plane), and further subjecting them a heat treatment (bonding heat treatment) for firmly bonding them to obtain an SOI wafer.
In this method, silicon wafers can be directly bonded together without interposing an oxide film. This method is used not only in the case of bonding the silicon wafers together, but also in the case of implanting ions into a silicon wafer to be bonded to an insulator wafer such as quartz, silicon carbide, and alumina having different thermal expansion coefficients. There has recently been also known a method for manufacturing an SOI wafer in which hydrogen ions are excited to perform ion implantation in a plasma state for separation at room temperature without adding a special heat treatment.
According to this method, the separated plane is a good mirror surface, and an SOI wafer having extremely high uniformity of the SOI layer can be obtained relatively easily.
Abe Takao
Miyajima Hajime
Okabe Keiichi
Takei Tokio
Greenblum & Bernstein P.L.C.
Lindsay Jr. Walter L.
Niebling John F.
Shin-Etsu Handotai & Co., Ltd.
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