Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1997-08-06
1998-11-17
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
216 38, 216 88, H01L 2100
Patent
active
058376119
ABSTRACT:
When large-scale integrated circuits are produced, pronounced differences in height occur within conductor track levels. Those extreme topographies lead to difficulties during photo-lithographic processes, since there is a direct relationship between resolution and depth of focus. A production method for applying an insulation layer functioning as an intermetal dielectric is based on an ozone-activated selective deposition of silicon oxide. The conductor tracks are completely encapsulated with an insulation layer, so that bulges do not occur above upper edges of the conductor tracks.
REFERENCES:
patent: 5674784 (1997-10-01), Jang et al.
patent: 5702980 (1997-12-01), Yu et al.
Global Planarization by Selective Deposition of Ozone/TEOS, E. Fischer et al., Siemens AG, Components Group, Munchen, Germany.
Applications of APCVD TEOS/O.sub.3 thin films in ULSI IC fabrication, H. Wallace Fry et al., Solid State Technology, Mar. 1994, pp. 31-40.
Gabric Zvonimir
Grassl Thomas
Spindler Oswald
Greenberg Laurence A.
Lerner Herbert L.
Powell William
Siemens Aktiengesellschaft
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