Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-09-13
2001-03-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S246000, C438S242000, C438S243000, C438S526000
Reexamination Certificate
active
06200873
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating a trench capacitor with an insulation collar.
Integrated circuits (ICs) or chips use capacitors for the purpose of storing charge. One example of an IC which uses capacitors to store charges is a memory IC, such as, for example, a chip for a dynamic read/write memory with random access (DRAM). The charge state (“0” or “1”) in the capacitor represents a data bit in this case.
A DRAM chip contains a matrix of memory cells which are connected up in the form of rows and columns. The row connections are usually referred to as word lines and the column connections as bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions separated by a channel above which a gate is arranged. Depending on the direction of the current flow, one diffusion region is referred to as the drain and the other as the source. The designations “drain” and “source” are used mutually interchangeably here with regard to the diffusion regions. The gates are connected to a word line, and one of the diffusion regions is connected to a bit line. The other diffusion region is connected to the capacitor. The application of a suitable voltage to the gate switches the transistor on and enables a current flow between the diffusion regions through the channel in order thus to form a connection between the capacitor and the bit line. The switching-off of the transistor disconnects this connection by interrupting the current flow through the channel.
The charge stored in the capacitor decreases with time on account of an inherent leakage current. Before the charge has decreased to an indefinite level (below a threshold value), the storage capacitor must be refreshed.
Ongoing endeavors to reduce the size of storage devices foster the design of DRAMs having a greater density and a smaller characteristic size, that is to say a smaller memory cell area. In order to fabricate memory cells which occupy a smaller surface region, smaller components, for example capacitors, are used. However, the use of smaller capacitors results in a reduced storage capacitance, which, in turn, can adversely affect the functionality and usability of the storage device. For example, sense amplifiers require a sufficient signal level for reliable read-out of the information in the memory cells. The ratio of the storage capacitance to the bit line capacitance is critical in determining the signal level. If the storage capacitance becomes too small, this ratio may be too small to generate a sufficient signal. Likewise, a smaller storage capacitance requires a higher refresh frequency.
One type of capacitor usually used in DRAMs is a trench capacitor. A trench capacitor has a three-dimensional structure formed in the silicon substrate. An increase in the volume or the capacitance of the trench capacitor can be achieved by etching more deeply into the substrate. In this case, the increase in the capacitance of the trench capacitor does not have the effect of enlarging the surface occupied by the memory cell.
A customary trench capacitor contains a trench etched into the substrate. This trench is typically filled with n+-doped polysilicon, which serves as one capacitor electrode (also referred to as storage capacitor). Optionally, a second capacitor electrode (also referred to as “buried plate”) is formed by outdiffusion of n
−
-type dopants from a dopant source into a region of the substrate which surrounds the lower portion of the trench. An n
+
-doped silicate glass, such as, for example, an arsenic-doped silicate glass (ASG), serves as the dopant source in this case. A storage dielectric containing nitride is usually used to insulate the two capacitor electrodes.
A dielectric collar is produced in the upper region of the trench in order to prevent a leakage current from the capacitor connection with the buried plate. The storage dielectric in the upper region of the trench, where the collar is to be formed, is removed before said collar is formed. The removal of the nitride prevents a vertical leakage current along the collar.
Although applicable to any desired trench capacitors, the present invention and the problems on which it is based will be explained below with regard to a trench capacitor used in a DRAM memory cell. Such memory cells are used in integrated circuits (ICs), such as, for example, random access memories (RAMs), dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), embedded DRAMs and read-only memories (ROMs). Other integrated circuits contain logic devices, such as, for example, programmable logic arrays (PLAs), application-specific ICs (ASICs), mixed logic/memory ICs (embedded DRAMs) or other circuit devices. It is usual for a multiplicity of ICs to be fabricated in parallel on a semiconductor substrate, such as, for example, a silicon wafer. After processing, the wafer is divided in order to separate the ICs into a multiplicity of individual chips. The chips are then packaged into end products, for example for use in consumer products such as, for example, computer systems, cellular telephones, personal digital assistants (PDAs) and further products. For discussion purposes, the invention will be described with regard to the formation of an individual memory cell.
In order to explain the problems on which the present invention is based, first of all a number of customary trench capacitor DRAM memory cells and also methods for fabricating them are explained below.
With reference to
FIG. 5
, a customary trench capacitor DRAM memory cell
100
is shown. It comprises a trench capacitor
160
formed in a substrate
101
. The substrate is lightly doped with p-type dopants (p−), such as e.g. boron (B). The trench
108
is usually filled with polysilicon
161
doped with n-type dopants (n+), such as e.g. arsenic (As) or phosphorus (P). A buried plate
165
, which is doped with As for example, is optionally provided in the substrate
101
in the vicinity of the lower region of the trench
108
. The As is diffused into the silicon substrate
101
for example from a dopant source, such as ASG for example, which is formed on the sidewalls of the trench
108
. The polysilicon
161
and the buried plate
165
serve as the capacitor electrodes.
A storage dielectric
164
isolates these capacitor electrodes. By way of example, the storage dielectric layer
164
comprises nitride or nitride/oxide. Oxide
itride/oxide or another dielectric layer or a stack of dielectric layers, such as, for example, oxide, nitride oxide or NONO, can likewise be used.
The DRAM memory cell
100
likewise has a transistor
110
. The transistor
110
comprises a gate
112
and diffusion regions
113
and
114
. The diffusion regions
113
,
114
, which are separated by a channel
117
, are formed by the implantation of n-type dopants, such as, for example, phosphorus (P). A capacitor connection diffusion region
125
, which is designated as “capacitor connection”, connects the trench capacitor
160
to the transistor
110
. The capacitor connection diffusion region
125
is formed by outdiffusion of dopants from the trench polysilicon
161
through a buried strap
162
.
A collar
168
is formed on an upper region of the trench
108
. The upper region of the trench
108
means the portion which contains the collar
168
, and the lower region of the trench means the portion below the collar
168
. The collar
168
prevents a leakage current of the capacitor connection
162
to the buried plate
165
. The leakage current is undesirable because it impairs the retention time of the memory cell, which increases the refresh frequency and therefore adversely affects the functionality.
A buried well
170
with n-type dopants, such as, for example, P or As, is provided below the surface of the substrate
101
Arnold Norbert
Schrems Martin
Greenberg Laurence A.
Keshavan Belur
Lerner Herbert L.
Siemens Aktiengesellschaft
Smith Matthew
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