Product-summing arithmetic circuit

Details Product-summing arithmetic circuit Product-summing arithmetic circuit

1996-09-10

1998-12-08

Moise, Emmanuel L.

Boots, shoes, and leggings

36472503, G06F 700, G06F 1500, G06F 1714

Patent

active

058479805

ABSTRACT:
In an IDCT circuit, a first RAC and a second RAC each have a ROM for sequentially generating a plurality of partial products and an accumulator for performing a digit-adjustment accumulation of the generated partial products while truncating the LSB of an intermediate accumulation result for every cycle. The first RAC further has a carry bit generator for holding a carry bit of one cycle before and for generating a carry bit of a current cycle by performing a majority arithmetic operation of the LSB of an intermediate accumulation result of the first RAC, the LSB of an intermediate accumulation result of the second RAC and the one-cycle-before carry bit. The second RAC further has a borrow bit generator for holding a borrow bit of one cycle before and for generating a borrow bit of a current cycle by performing a majority arithmetic operation of the LSB of an intermediate accumulation result of the first RAC, an inverted bit of the LSB of an intermediate accumulation result of the second RAC and the one-cycle-before borrow bit. A final accumulation result of the first RAC, a final accumulation result of the second RAC, a final carry bit and a final borrow bit are used in butterfly arithmetic operations.

REFERENCES:
patent: 4791598 (1988-12-01), Liou et al.
patent: 5053985 (1991-10-01), Kao
patent: 5204830 (1993-04-01), Wang et al.
patent: 5307375 (1994-04-01), Wu et al.
patent: 5442579 (1995-08-01), Thomson
patent: 5457646 (1995-10-01), Jang et al.
patent: 5483475 (1996-01-01), Friedlander et al.

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