Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2000-02-22
2001-07-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S455000, C148S033000, C156S153000
Reexamination Certificate
active
06261928
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the production of a microstructure or a nanostructure on a substrate.
BACKGROUND OF THE INVENTION
1. Field of the Invention
2. Discussion of the Background
Ever smaller sizes, are in the form of a lattice of microvolumes of material obtained on the surface of a substrate. By microvolume is meant for example volumes of parallelepiped shape preferably less than one micrometer in size.
Generally, interest is focused on microstructures in semiconductor material, in particular in silicon, in AsGa, in III-V compounds and SiC. However there is also interest in conductor materials, such as metals, and in dielectric materials such as SiO2.
These micro- or nanostructures are intended for the production of electronic, optic or optoelectronic devices. In particular, with these types of structures it is possible to produce a network of quantum dots, or electronic devices called mono-electrons, or Coulomb blockade electronic devices, or even light-emitting devices.
If it is desired to produce microstructures, techniques are used that are nowadays conventional in the area of micro-electronics. In particular, the principles of lithography combined with dry or wet etching operations are used, or ion implantation, depositing, or heat treatment. For example, if it is desired to produce a square network of parallelepiped microvolumes in monocrystalline silicon, with each microvolume having a side length of 1 &mgr;m and a thickness of 0.2 &mgr;m, the microvolumes being separated by a distance of 0.5 &mgr;m, it is possible to use a SOI wafer (Silicon-on-Insulator) having a monocrystalline silicon layer 0.2 &mgr;m thick. To the wafer silicon layer is applied a photosensitive resin layer which is insulated by means of an Electron Beam Pattern Generator such as to pattern the resin with a matrix of lines and columns 0.5 &mgr;m wide representing the spaces in between the microvolumes. Resin development, to develop the exposed parts, uncovers the silicon layer corresponding to the matrix of lines and columns. The wafer is then subjected to plasma etching for selective removal of the silicon in relation to the resin. The etching operation is completed when the underlying silicon layer is reached. After removing the resin, a network of microvolumes is obtained each 1 &mgr;m×1 &mgr;m×0.2 &mgr;m in size and spaced at 0.5 &mgr;m intervals. If necessary, the spaces between the microvolumes may then be filled in with a dielectric layer such as SiO
2
, either using a heat oxidation process or a depositing process of CVD type.
A network of microvolumes may also be produced by lithography using an interferometry or holography technique, such as disclosed by the article: “Scalable Fabrication and Optical Characterization of nm Si Structures” by S. H. ZAIDI et al., published in Mat. Res. Soc. Symp. Proc. Vol. 358, pages 957-968, Materials Research Society.
With the use of these techniques it is possible to produce microstructures for sizes of the order of one micrometer or a few tenths of a micrometer. To obtain the best resolution in terms of lithography, electron beam pattern generation is used or a photo repeater operating at a wavelength of 248 nm or 193 nm.
To produce microstructures with much smaller-sized microvolumes (for example a few tenths of a nanometer), no known means are available if it is desired, in economically acceptable manner and on large surfaces, to obtain microstructures arranged in a pre-determined plan of arrangement.
It is to be noted however that it is possible to produce microvolumes in a first material inside a matrix of a second material, for example by using ion implantation to insert atoms of the first material in this matrix, their concentration being such and applied heat treatment being such that these atoms collect as precipitates inside the matrix. In this way it is possible to obtain precipitates of silicon in a SiO
2
matrix of the order of 10 nm. Said technique is described for example in the article “Control of and Mechanisms for Room Temperature Visible Light Emission from Silicon Nanostructures in SiO
2
, formed by Si
+
Ion Implantation” by T. KOMODA et al., published in Mat. Res. Soc. Symp. Proc. Vol. 358, pages 163-168, 1995, Materials Research Society. However, the precipitates obtained are distributed randomly in the matrix.
In similar fashion, by making a deposit (for example by evaporation) on a surface, it is possible to obtain cores of condensation randomly distributed on the surface. The article “Generation and Structural Analysis of Silicon Nanoparticles” by PING LI and K. SATTLER, published in Mat. Res. Soc. Symp. Proc. Vol. 358, pages 123-126, 1995, Materials Research Society, discloses the evaporation of silicon on a silicon or graphite surface.
The applications of these microstructures are multiple and depend upon the particular properties of each one. These properties relate to a size effect on the electronic status of the carriers in these materials, to surface and interface effects, to the existence or not of intergranular phases, etc. One particular application is the production of light emitters, especially from materials such as silicon which, in the solid monocrystalline state, are not light-emitting (see the article by T. KOMOKA cited above). A further application is the production of electronic devices based on the quantum confinement of electronic conductors in the microvolumes of the structure or on Coulomb blockade effects. This application is described in the article “Modelling the Multiplicity of Conductance Structures in Clusters of Silicon Quantum Dots” by D. W. BOERINGER and R. TSU, published in Mat. Res. Soc. Symp. Proc. Vol. 358, pages 569-574, 1995, Materials Research Society.
SUMMARY OF THE INVENTION
The present invention was designed to enable the production of microstructures able to contain microvolumes of much smaller size than the microvolumes which can currently be produced, for example a few tenths of a nm, in economic manner and on large surfaces. In addition, these microstructures are arranged according to a predetermined plan instead of being distributed at random.
The invention puts forward a method for producing micro or nanostructures, which can be applied to crystalline materials whether semiconductor, conductor or dielectric.
The subject matter of the invention is therefore a method for producing a micro or nanostructure on a substrate, characterized in that it entails the following steps:
bonding by placing one surface of a first wafer in crystalline material in contact with one surface of a second wafer in crystalline material, such that the crystalline lattices presented by the said surfaces offer at least one mismatch parameter able to allow the formation of a lattice of crystalline defects and/or a lattice of strains within a crystalline zone extending either side of the interface of the two wafers, at least one of said lattices determining the micro or nanostructure,
thinning one of the two wafers to expose the lattice defects and/or the lattice strains on a substrate formed by the other wafer.
The mismatch parameter may be formed by a determined angle of rotational shift in the crystalline lattices presented by said surfaces. The lattice of defects obtained, so-called “twist” lattice, is a lattice of screw dislocations.
The mismatch parameter may also be formed by a difference in crystalline mesh parameter between the crystalline materials of the surfaces of the contacted wafers. The lattice deformation obtained is called a “misfit”.
The mismatch parameter may also be formed by a determined angle under which the surface of at least one of the wafers is shifted in relation to the ordinary crystallographic plane of direction corresponding to this surface. The disoriented crystalline surfaces (one only or both) in relation to an ordinary crystallographic plane are called vicinal. The lattice deformation is then called a “miscut”.
All combinations of mismatch parameters are possible, for example by bonding two different materials with shifted rotation.
Blum David S
Bowers Charles
Commissariat a l 'Energie Atomique
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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