Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
2007-08-07
2007-08-07
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C709S217000
Reexamination Certificate
active
11055297
ABSTRACT:
A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
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Clark Leo J.
Fields, Jr. James S.
Guthrie Guy L.
Starke William J.
Stuecheli Jeffrey A.
Dillon & Yudell LLP
Gerhardt Diana R.
Kim Kenneth S.
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