Processor with word-aligned branch target in a byte-oriented ins

Details Processor with word-aligned branch target in a byte-oriented ins Processor with word-aligned branch target in a byte-oriented ins

1994-09-16

1996-12-31

Geckil, Mehmet B.

395380, 395500, G06F 900

Patent

active

055903584

ABSTRACT:
A microcontroller or processor architecture that performs word aligned multi-byte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with a complete return address which is byte aligned.

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patent: 5051885 (1991-09-01), Yates, Jr. et al.
patent: 5249273 (1993-09-01), Yoshitake et al.
patent: 5327536 (1994-07-01), Suzuki
patent: 5335332 (1994-08-01), Christopher, Jr. et al.
patent: 5381532 (1995-01-01), Suzuki

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