Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2007-07-17
2007-07-17
Pham, Chi (Department: 2616)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S411000
Reexamination Certificate
active
10085222
ABSTRACT:
A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements. The interval computation element operates under software control in at least one of determining and adjusting the transmission interval, and may be operative to determine periodically if the transmission interval requires adjustment in order to maintain the desired service level for one or more of the transmission elements.
REFERENCES:
patent: 5694554 (1997-12-01), Kawabata et al.
patent: 5712851 (1998-01-01), Nguyen et al.
patent: 5889763 (1999-03-01), Boland et al.
patent: 6011775 (2000-01-01), Bonomi et al.
patent: 6011798 (2000-01-01), McAlpine
patent: 6374405 (2002-04-01), Willard
patent: 6377583 (2002-04-01), Lyles et al.
patent: 6389019 (2002-05-01), Fan et al.
patent: 6414963 (2002-07-01), Gemar
patent: 6477144 (2002-11-01), Morris et al.
patent: 6526062 (2003-02-01), Milliken et al.
patent: 6535512 (2003-03-01), Daniel et al.
patent: 6603766 (2003-08-01), Zifroni et al.
patent: 6661774 (2003-12-01), Lauffenburger et al.
patent: 6667977 (2003-12-01), Ono
patent: 6721325 (2004-04-01), Duckering et al.
patent: 6735207 (2004-05-01), Prasad et al.
patent: 2002/0080721 (2002-06-01), Tobagi et al.
patent: 2002/0122403 (2002-09-01), Hashem et al.
patent: 2002/0142780 (2002-10-01), Airy et al.
patent: 2002/0159411 (2002-10-01), Airy et al.
patent: 2003/0021228 (2003-01-01), Nakano et al.
patent: 2003/0046414 (2003-03-01), Pettyjohn et al.
patent: 2003/0081624 (2003-05-01), Aggarwal et al.
patent: 2005/0050543 (2005-03-01), Ogus et al.
Kramer David B.
Sonnier David P.
Agere Systems Inc.
Pham Chi
Tsegaye Saba
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