Modulators – Pulse or interrupted continuous wave modulator – Pulse width modulator
Reexamination Certificate
2001-06-01
2003-04-22
Pascal, Robert (Department: 2817)
Modulators
Pulse or interrupted continuous wave modulator
Pulse width modulator
C327S172000, C327S175000
Reexamination Certificate
active
06552625
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a processor having a pulse width modulation (PWM) generator that has multiple fault inputs that force the PWM output signals to defined states and priority logic that outputs a fault response associated with a highest priority fault inputs, in the case of multiple concurrent faults.
BACKGROUND OF THE INVENTION
Processors, including microprocessors, digital signal processors and microcontrollers, operate by running software programs that are embodied in one or more series of program instructions stored in a memory. The processors run the software by fetching the program instructions from the series of program instructions, decoding the program instructions and executing them. In addition to program instructions, data is also stored in memory that is accessible by the processor. Generally, the program instructions process data by accessing data in memory, modifying the data and storing the modified data into memory.
Processors may be programmed to perform a wide variety of functions in software. In some cases, however, dedicated hardware may be included in a processor that significantly eases the processing load needed to perform certain functions. This allows the use of lower performance processor for these functions, which lowers the cost of the processor. One type of dedicated hardware that may advantageously be included in a processor is power control hardware. Power control hardware provides the capability to control circuitry and devices that use significant amounts of power. For example, power control hardware may be used to control motors, power supplies, etc.
One common mode of operation of power control hardware is pulse width modulation (PWM). In PWM, the power level is controlled by controlling the duty cycle of a signal that has only two states—active and inactive. The signal is then integrated in a device, such as a motor or a capacitor, to yield the equivalent of a continuously varying voltage and current.
One problem that arises when PWM hardware is included in a processor is handling fault conditions that may occur in the external, controlled circuitry. Examples of faults that may occur include failure of an external switching device, such as a transistor, short circuit of external circuitry or devices, such as a motor, overcurrent detected in external circuitry, a fault in the power supply, etc. Typically, fault conditions must be dealt with quickly, in order to avoid catastrophic failures. An additional problem arises when more than one fault conditions occurs concurrently. Problems arise with conventional PWM hardware, which has been included in current processors, in dealing with fault conditions, and particularly in dealing with multiple concurrent fault conditions.
A need arises for a technique that provides an improved ability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor.
SUMMARY OF THE INVENTION
The present invention is a processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. This is accomplished by providing multiple fault inputs that force the PWM output signals to defined states and priority logic that outputs a fault response associated with a highest priority fault inputs, in the case of multiple concurrent faults.
According to one embodiment of the present invention, a pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.
In one aspect of the present invention, each fault input has an associated defined state to which the pulse width modulation output will be driven. Values defining the states of the pulse width modulation outputs may be stored in at least one register modifiable by software.
In one embodiment of the present invention, a processor includes pulse width modulation generation circuitry including fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.
In one aspect of the present invention, each fault input has an associated defined state to which the pulse width modulation output will be driven. Values defining the states of the pulse width modulation outputs may be stored in at least one register modifiable by software.
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Glenn Kimberly E
Microchip Technology Inc.
Swidler Berlin Shereff & Friedman, LLP
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