Processor with multiple microprogrammed processing units

Details Processor with multiple microprogrammed processing units Processor with multiple microprogrammed processing units

1993-09-27

1995-04-18

Harrell, Robert B.

Boots, shoes, and leggings

395800, 3649283, 3649302, 3642306, 3642817, G06F 900, G06F 1516

Patent

active

054086230

ABSTRACT:
A data processing system having processors with large instruction sets comprises a plurality of microprogrammed execution units (EAD, BDP, FPP), which communicate with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BOP). A third unit is a floating point calculation unit (FPP). To permit the units to function autonomously, each unit includes its own command block and synchronizing means to authorize or interrupt the execution of the microprogram defined by the instruction in progress in each unit. These synchronizing means interrupt said execution if:
either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit,
or a result expected by said unit and calculated by another unit is not effectively received by said unit,
or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result.

REFERENCES:
patent: 4636942 (1987-01-01), Chen et al.
patent: 5016163 (1991-05-01), Jesshope et al.
IEEE Transactions on Computers, vol. C-27, No. 3, Mar. 1978 pp. 270-275; L. C. Higbie.

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