Processor with a control instruction for sending control...

Details Processor with a control instruction for sending control... Processor with a control instruction for sending control...

1998-12-23

2002-05-14

Kim, Kenneth S. (Department: 2183)

Electrical computers and digital processing systems: processing

Architecture based instruction processing

C712S227000

Reexamination Certificate

active

06389528

ABSTRACT:

TECHNICAL FIELD
This invention relates to computer processors, and more particularly, to a processor that is adaptable according to users preferences.
BACKGROUND OF THE INVENTION
A reference book on processor architectures is, for example, L. Ciminiera and A. Valenzano, “Advanced Microprocessor Architectures”, Addison-Wesley, 1987, wherein both traditional and advanced architectures, such as CISC (Complex Instruction Set) and RISC (Reduced Instruction Set) configurations, are illustrated.
In fact, to enhance the calculating capabilities of processors, there are two opposite courses that can be followed: a first course consists of providing the processors with plural complex instructions (CISC), quite powerfull but slow to execute, and the second consists of providing the processors with few simple instructions (RISC), less powerful but quickly executed.
An obvious solution is that of making each instruction the most convenient compromise (of instruction complexity versus speed of execution) for the user of the processor. However, this cannot be carried into effect exhaustively, and in consequence, different processors are offered on the market for different types of applications.
SUMMARY OF THE INVENTION
An embodiment of this invention solves the problem outlined above by providing a processor with a set of instructions which can be easily expanded and/or customized by the user.
The processor of the embodiment is provided with at least one control instruction wherein the operand section represents control signals for controlling the processor operation; in this way, an extension of the set of instructions can be simulated.
Accordingly, the control unit of the processor of the embodiment is capable of coupling its outputs to its inputs, upon receiving an instruction as above, so as to transfer such internal operation control signals without any interpretation.
According to another aspect, another embodiment of the invention is directed to an integrated circuit and a processing system in which the processor can be advantageously included.


REFERENCES:
patent: 5440747 (1995-08-01), Kiuchi
patent: 6076156 (2000-06-01), Pickett et al.
patent: WO 91/11765 (1991-08-01), None
Béraud and Esteban, “Microprocessor operation code expander,”IBM Technical Disclosure Bulletin 20(12): 5197-5199, May 1978.
“Selecting Predecoded Instructions with a Surrogate,”IBM Technical Disclosure Bulletin 36(6A): 35-38, Jun. 1993.
Forsell, “Minimal Pipeline Architecture—An Alternative to Superscalar Architecture,”Microprocessors and Microsystems 20(5): 277-284, Sep. 1996.
Dirac, “Control Word Expansion,”IBM Technical Disclosure Bulletin 3(7): 23, Dec. 1960.

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