Processor which returns from a subroutine at high speed and...

Details Processor which returns from a subroutine at high speed and... Processor which returns from a subroutine at high speed and...

1996-01-22

2001-01-09

Oberley, Alvin E. (Department: 2755)

Reexamination Certificate

active

06170998

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a processor, and an apparatus for translating a source program written in a programming language into a machine program suitable for the processor.
(2) Description of the Related Art
Recently, information apparatuses with a built-in micro processor have been developed to respond to various needs. The development of these information apparatuses is focused on speeding up their process and reducing their cost from both hardware and software.
In the software, the process is expressed by using many subroutines which are nested to several levels. In order to call a subroutine, a return address is stored on a stack, and in order to return to the original program from the subroutine, the return address is moved from the stack to a program counter.
The time to access the stack to fetch the return address is ignorable when a program has only a few subroutine calls; however, when there are dozens of subroutine calls, the access time of the stack causes delays in the operations of the processor.
In order to avoid the delays to be caused by the access time of the stack, a conventional processor is provided with a register specifically designed to store a return address. The register is hereinafter referred to as the return-address-only register.
FIG. 1
shows a list of instructions to be used in the conventional processor. In the list, SP, @SP, and FR represent a stack pointer, a reference to a stack, and the return-address-only register, respectively.
The instruction: jsr _f is a subroutine call instruction, and indicates that a return address is stored not only on a stack like an ordinary subroutine call instruction but also in the return-address-only register. When the processor has fetched a subroutine call instruction from a stack, the processor subtracts 2 from a stack pointer value, and stores the address of an instruction which immediately follows the subroutine call instruction on the stack which is indicated by the stack pointer and in the return-address-only register.
The instruction: rts is a return instruction, and indicates that a return address on a stack is moved to a program counter, 2 is added to the stack pointer value, and the processor returns to the original program in the same manner as an ordinary return instruction.
The instruction: rtsfr is also a return instruction, but indicates that a return address is moved not from the stack but from the return-address-only register to the program counter. Such an instruction as obtains a return address from a stack is referred to as a special return instruction.
The other instructions on the list such as an add instruction and a mu
1
instruction are not explained because they are not directly related to the present invention.
The operations of the processor provided with the return-address-only register to jump to a subroutine and to return from a subroutine will be described with reference to
FIGS. 2 and 3
.
FIG. 2
shows a list of output codes of an assembler program, and the entrance locations of functions are labeled with either _main, _f
1
, or _f
2
. Hereinafter, functions are referred to subroutines.
In the program, a special return instruction exists at the end of a function which involves no function call. In other words, it exists in a function which is located at the deepest level of nesting. This is because the return-address-only register stores only one return address while a stack is organized on a First In-Last Out basis.
The instructions are assigned respective addresses such as 0100 or 0101 shown on the left and respective identifiers (ex
1
)-(ex
16
) shown on the right.
FIG. 3
shows a flowchart which depicts how the conventional processor calls a subroutine and returns from a subroutine.
It is assumed that the address 0100 of the instruction with (ex
1
) is set at the program counter.
At u
1
, whether there is a next instruction to be fetched is determined. If there is, the process proceeds to u
2
and otherwise terminates the process. Since the next instruction with (ex
1
) exists in this case, the process proceeds to u
2
, and further proceeds to u
3
, u
4
, and u
5
to execute the instruction with (ex
1
), and the process returns to u
1
. At u
1
, it is determined that there is a next instruction to be fetched. At u
2
, the instruction with (ex
2
) is fetched. At u
3
, whether the instruction is a function call instruction is determined. If it is, the process proceeds to u
6
and otherwise proceeds to u
4
. Since the instruction with (ex
2
): jsr _f
1
is a function call instruction, the process proceeds to u
6
. At u
6
, the address 0102 of the next instruction with (ex
3
) is stored on the stack as a return address. At u
7
, the address 0102 is also stored in the return-address-only register, and a function f
1
is called. Then, the process returns to u
1
to fetch and execute the consecutive instructions with (ex
6
) and (ex
7
) of the function f
1
.
After the execution of the instruction with (ex
7
), it is determined that the next instruction with (ex
8
) exists at u
1
and the instruction with (ex
8
) is fetched at u
2
. It is determined that the instruction with (ex
8
): jsr _f
2
is a function ca
1
instruction at u
3
, and the address 0108 of the next instruction with (ex
9
) is stored on the stack as a return address at u
6
. The address 0108 is also stored in the return-address-only register, and the function f
2
is called at u
7
.
The consecutive instructions with (ex
10
)-(ex
12
) of the function f
2
are fetched and executed at u
1
-u
5
.
After the execution of the instruction with (ex
12
), it is determined that the next instruction with (ex
13
) exists at u
1
and the instruction is fetched at u
2
. It is determined that the instruction with (ex
13
) is not a function ca
1
instruction at u
3
, and the process proceeds to u
4
. At u
4
, whether the instruction with (ex
13
) is a special return instruction is determined. If it is, the process proceeds to u
8
and otherwise proceeds to u
5
. Since the instruction with (ex
13
): rtsfr is a special return instruction, the process proceeds to u
8
. At u
8
, the address 0108 of the next instruction with (ex
9
) is moved from the return-address-only register to the program counter, and as a result, the function f
1
is resumed without access to a stack.
Then, it is determined at u
1
that the return instruction with (ex
9
) exists, and the instruction is fetched at u
2
. The process proceeds to u
3
, u
4
, and u
5
where the return instruction with (ex
9
) is executed. That is, the processor accesses the stack and fetches the address 0102 of the instruction with (ex
3
) and exits from the function f
1
.
Since the next instruction with (ex
4
):jsr _f
3
is a function call instruction, the address 0104 of the next instruction with (ex
5
) is stored on the stack at u
6
, and also stored in the return-address-only register to call the function f
3
at u
7
. Then, the consecutive instructions with (ex
14
) and (ex
15
) are fetched and executed at u
1
-u
5
. The next instruction with (ex
16
): rtsfr is fetched at u
2
and the address 0104 of the next instruction (ex
5
) is moved from the return-address-only register to the program counter to return to the function f
1
at u
8
.
As explained hereinbefore, the conventional processor provided with the return-address-only register exits from a subroutine and returns to the original program, by making use of the return-address-only register instead of accessing to a stack in the case where there is a special return instruction.
As a result, the speed of returning from a subroutine is heightened.
However, the conventional processor provided with the return-address-only register still has a drawback that its circuit must be large to have enough space to accommodate the return-address-only register.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a processor which returns from a subroutine at a high speed without providing a return-address-only register.
A second object of the p

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