Patent
1997-03-18
1999-03-16
Treat, William M.
395392, G06F 938, G06F 928
Patent
active
058840605
ABSTRACT:
An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.
REFERENCES:
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5640588 (1997-06-01), Vegesna et al.
Avula Jayachandra B.
Jewett Peter H.
Monaco James E.
Mundkur Yatin G.
Naik Vinay J.
Caldwell Andrew
Ross Technology, Inc.
Strawbrich, Esq. Robert C.
Treat William M.
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