Processor to peripheral interface for asynchronous or synchronou

Details Processor to peripheral interface for asynchronous or synchronou Processor to peripheral interface for asynchronous or synchronou

1987-02-12

1988-11-15

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

375 8, 375114, H04L 702

Patent

active

047854693

ABSTRACT:
There is disclosed herein an interface for a peripheral to allow the peripheral to communicate with either synchronous or asynchronous systems. The interface includes a series of flip-flops coupled in a chain to take the combined data strobe and chip select signals from an asynchronous system such as a microprocessor and synchronize the combined signal with the peripheral clock and convert the signal to a pulse. This pulse then emulates the instruction enable pulse received from synchronous microprogrammed systems. If the peripheral is operating in a synchronous sytem, the instruction enable signal from the system is gated through a multiplexer controlled by a mode signal which indicates which mode is active so as to act as the peripheral instruction enable signal. An AND gate gates one bit of the instruction bus with the ANDed chip select and data strobe signals to create a read/write control signal for internal use in controlling the data bus drivers.

REFERENCES:
patent: Re31319 (1983-07-01), Fraser
patent: 4093823 (1978-06-01), Chu
patent: 4384307 (1983-05-01), Kuzmik et al.
patent: 4581483 (1986-04-01), Ralston
patent: 4656643 (1987-04-01), Geneste et al.
patent: 4700358 (1987-10-01), Duncanson et al.
AM9517A Multimode DMA Controller, Jun. 1982.

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