Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2010-06-08
2011-11-29
Nguyen, Phu (Department: 2628)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S530000, C709S231000, C709S248000, C712S010000, C712S023000, C712S032000
Reexamination Certificate
active
08068109
ABSTRACT:
Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs. The two or more outputs are associated into one or more groups. Each group is less than or equal to a target data size associated with a subsequent process.
REFERENCES:
patent: 3496551 (1970-02-01), Driscoll et al.
patent: 5185694 (1993-02-01), Edenfield et al.
patent: 5452452 (1995-09-01), Gaetner et al.
patent: 5592671 (1997-01-01), Hirayama
patent: 5745778 (1998-04-01), Alfieri
patent: 5794017 (1998-08-01), Evans et al.
patent: 5832262 (1998-11-01), Johnson et al.
patent: 6003112 (1999-12-01), Tetrick
patent: 6144986 (2000-11-01), Silver
patent: 6279040 (2001-08-01), Ma et al.
patent: 6289369 (2001-09-01), Sundaresan
patent: 6370681 (2002-04-01), Dellarocas et al.
patent: 6665699 (2003-12-01), Hunter et al.
patent: 6665783 (2003-12-01), Zahir
patent: 6728959 (2004-04-01), Merkey
patent: 7058750 (2006-06-01), Rankin et al.
patent: 7127477 (2006-10-01), Duncombe et al.
patent: 7236738 (2007-06-01), Settle
patent: 7236998 (2007-06-01), Nutter et al.
patent: 7298377 (2007-11-01), Fossum et al.
patent: 7304646 (2007-12-01), Iwata
patent: 7321958 (2008-01-01), Hofstee et al.
patent: 7522168 (2009-04-01), Stenson et al.
patent: 7734827 (2010-06-01), Iwamoto
patent: 7760206 (2010-07-01), Stenson et al.
patent: 2002/0138637 (2002-09-01), Suzuoki et al.
patent: 2004/0054883 (2004-03-01), Goodman et al.
patent: 2005/0091473 (2005-04-01), Aguilar et al.
patent: 2005/0188372 (2005-08-01), Inoue et al.
patent: 2005/0188373 (2005-08-01), Inoue et al.
patent: 2007/0074206 (2007-03-01), Iwamoto
patent: 2007/0074207 (2007-03-01), Bates et al.
patent: 2007/0074212 (2007-03-01), Bates et al.
patent: 2007/0074221 (2007-03-01), Stenson et al.
patent: 2007/0083755 (2007-04-01), Iwamoto
patent: 2007/0198628 (2007-08-01), Bates et al.
patent: 0 806 730 (1997-11-01), None
patent: 2394336 (2004-04-01), None
patent: 10040414 (1998-02-01), None
patent: WO 97/06484 (1997-02-01), None
patent: WO 02/091180 (2002-11-01), None
patent: WO 2004/084069 (2004-09-01), None
Sony Computer Entertainment Incorporated, “Cell Broadband Engine Architecture”, Version 1.0, Aug. 8, 2005.
Pratit Santiprabhob et al. “Fuzzy Rule-Based Process Scheduling Method for Critical Distributed Computing Environment”—Proceedings 2003 IEEE, Mar. 8, 2003, vol. 5, pp. 52267-52276.
J.A. Kahle et al. “Introduction to the Cell Multiprocessor” IBM Journal of Research and Development, vol. 49, No. 4-5. Jul. 2005, pp. 589-604.
George M. Candea et al. “Vassal: Loadable Scheduler Support for Multi-Policy Scheduling” Proceedings of the Usenix Window NT Symposium, Aug. 1998, pp. 157-166.
Alexandre E. Eichenberger et al., “Optimizing Compiler for a Cell Processor”, Proceedings of 14thInternational Conference on Parallel Architectures and Compilation Techniques, 2005 (PACT '05), pp. 161-172.
B. Flachs et al., “A Streaming Processing Unit for a Cell Processor”, 2005 IEEE International Solid-State Circuits Conference—Digest of Technical Papers, pp. 134-135.
Scott Whitman, “Dynamic Load Balancing for Parallel Polygon Rendering”, IEEE Computer Graphics and Applications, vol. 14, No. 4, Jul. 1994, pp. 41-48.
Jaspal Subhlok, et al., “Communication and Memory Requirements as the Basis for the Mapping Task and data Parallel Programs”, Supercomputing '94, Proceedings Washington, DC, 1994 IEEE, pp. 330-339.
Alan Heinrich, “Optimal Automatic Multi-Pass Shader Partitioning by Dynamic Programming”, Graphics Hardware (2005), p. 91-98.
D S Milojicic et al., “Process Migration” ACM Computing Surveys, ACM, New York, NY, US, vol. 32, No. 3, Sep. 2000-2009, pp. 241-299, XP002254767 ISSN: 0360-0300.
K Chanchio et al., “Data Collection and Restoration for Heterogeneous Process Migration” Software Practice & Experience, Wiley & Sons, Bognor Regis, GB, vol. 32, No. 9, Jul. 25, 2002, pp. 845-871, XP001115308 ISSN: 0038-0644.
Williams et al., “The Potential of the Cell Processor for Scientific Computing”, Conference on Computing Frontiers, ACM, 2006, pp. 9-20.
Gschwind, “Chip Multiprocessing and the Cell Broadband Engine”, Conference on Computing Frontiers, ACM, 2006, pp. 1-8.
Shinji, Kondo “Architecture of CELL processors; toward first-generation digital home”, Toshiba Review, Jul. 1, 2005, vol. 60, No. 70, pp. 48-51 (Kigyou Gihou 2006-00015-007).
“<Deciphering design idea> Ever-changing evolution by an embedded gene”, Nikkei Electronics, Nikkei BP, Feb. 28, 2005, No. 894, pp. 100-109 (domestic technical journals 2005-01100-001).
Concise explanation for ““<Deciphering design idea> Ever-changing evolution by an embedded gene”, Nikkei Electronics, Nikkei BP, Feb. 28, 2005, No. 894, pp. 100-109 (domestic technical journals 2005-01100-001)”.
Bates John P.
Stenson Richard B.
Isenberg Joshua D.
JDI Patent
Nguyen Phu
Sony Computer Entertainment Inc.
LandOfFree
Processor task and data management does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor task and data management, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor task and data management will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4276339