Processor system with writeback cache using writeback and non wr

Details Processor system with writeback cache using writeback and non wr Processor system with writeback cache using writeback and non wr

1993-03-22

1994-05-31

Dixon, Joseph L.

Boots, shoes, and leggings

36424341, 36424345, 3642545, 364DIG1, G06F 1300

Patent

active

053177207

ABSTRACT:
A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

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