Processor system including an index buffer circuit and a transla

Details Processor system including an index buffer circuit and a transla Processor system including an index buffer circuit and a transla

1993-02-01

1997-07-01

Lane, Jack A.

G06F 1210

Patent

active

056447485

ABSTRACT:
An index buffer circuit and a translation look-aside buffer (TLB) are provided in an address unit of a vector processor unit. The index buffer circuit incudes a plurality of buffers, an input pointer generating unit for generating an input control signal indicating which selected buffer in a buffer portion, index data shall be stored, and an output pointer generating unit for outputting a control signal indicated from which selected buffer in the buffer portion output data is to be read. The TLB translates a logical address to a physical address upon receipt of the output from the index buffer. The TLB has a least recently used (LRU) flag register which can maintain the priority even if the entries are reset and thus the entries of the TLB can be used as buffers when the vector processor unit operates as a bus slave.

REFERENCES:
patent: 4910668 (1990-03-01), Okamoto et al.
patent: 4945548 (1990-07-01), Iannarone et al.
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 5083269 (1992-01-01), Syobatake et al.

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