Patent
1995-06-07
1997-09-30
Treat, William M.
395563, G06F 746
Patent
active
056734263
ABSTRACT:
An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in program control order for execution. The issued instructions include floating point instructions and non-floating point instructions. The execution means executes the issued instructions such that at least the floating point instructions may be executed out of program control order by the execution means. The floating point exception unit includes a data storage structure including storage elements. Each issued instruction corresponds to one of the storage elements. Each storage element has a floating point instruction identifying field and a floating point trap type field. The floating point exception unit also includes first logic to write, for each issued instruction, data in the floating point instruction identifying field of the corresponding storage element which indicates whether or not the corresponding issued instruction is a floating point instruction. It further includes second logic to write, for each issued floating point instruction which causes during execution one or more floating point execution exceptions that will result in a corresponding one of a plurality of predefined types of floating point execution traps, data in the floating point trap type field of the corresponding storage element which identifies the one of the predefined types of floating point execution traps that will result. The precise state means retires each issued instruction which does not cause an execution exception during execution and for which all issued instructions preceding it in program control order have been retired. When a first one of the predefined execution exceptions is caused by an issued instruction, the execution means continues execution of issued instructions and the precise state means engages in execution trap sequencing by continuing to retire issued instructions until it encounters an issued instruction that cannot be retired. The issued instruction that cannot be retired being one of (a) the issued instruction that caused the first execution exception, and (b) an issued instruction that was issued earlier than the issued instruction that caused the first execution exception but which caused a second execution exception occurring later than the first execution exception. The floating point status register has a floating point trap type field. The writing means writes data to the floating point trap type field of the floating point status register which identifies the type of floating point execution trap identified by the data in the floating point trap type field of the storage element corresponding to the instruction that cannot be retired when the data in the floating point identifying field of the storage element corresponding to the instruction that cannot be retired indicates that the instruction that cannot be retired is a floating point instruction.
REFERENCES:
patent: 4703481 (1987-10-01), Fremont
patent: 4847755 (1989-07-01), Morrison et al.
patent: 4893233 (1990-01-01), Denman et al.
patent: 4903264 (1990-02-01), Talgam et al.
patent: 4912707 (1990-03-01), Kogge et al.
patent: 4956767 (1990-09-01), Stephenson
patent: 5003458 (1991-03-01), Yamaguchi et al.
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5021945 (1991-06-01), Morrison et al.
patent: 5053987 (1991-10-01), Genusov et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5093908 (1992-03-01), Beacom et al.
patent: 5193206 (1993-03-01), Mills
patent: 5235700 (1993-08-01), Alaiwan et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5271013 (1993-12-01), Gleeson
patent: 5293499 (1994-03-01), Jensen
patent: 5301309 (1994-04-01), Sugano
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5313647 (1994-05-01), Kaufman et al.
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5463745 (1995-10-01), Vidivans et al.
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5481685 (1996-01-01), Nguyen et al.
patent: 5497499 (1996-03-01), Garg et al.
Mike Johnson, Superscalar Microprocessor Design, 1991.
Shebanow Michael C.
Shen Gene W.
Szeto John
HaL Computer Systems, Inc.
Treat William M.
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