Processor resetting method and apparatus

Details Processor resetting method and apparatus Processor resetting method and apparatus

1993-07-07

1996-12-03

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

H04L 1256

Patent

active

055815499

ABSTRACT:
In a communication network including a plurality of nodes, when it is desired for a processor A of one of the nodes to reset another processor B within the same node or within another of the nodes, the processor A side generates a reset cell and transmits it to the party processor B side through a channel. The party processor B side confirms that the received cell is a reset cell, accepts the cell, and outputs a reset signal to the processor B to reset the processor B.

REFERENCES:
patent: 5163057 (1992-11-01), Grupp
patent: 5168497 (1992-12-01), Ozaki et al.
patent: 5251204 (1993-10-01), Izawa et al.
patent: 5271000 (1993-12-01), Engbersen et al.
patent: 5339314 (1994-08-01), Tanaka et al.
patent: 5339317 (1994-08-01), Tanaka et al.
patent: 5392286 (1995-02-01), Tanaka et al.

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