Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2011-02-01
2011-02-01
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C713S330000
Reexamination Certificate
active
07882334
ABSTRACT:
A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
REFERENCES:
patent: 4743864 (1988-05-01), Nakagawa et al.
patent: 4843300 (1989-06-01), Alderman
patent: 5652729 (1997-07-01), Iwata et al.
patent: 5777347 (1998-07-01), Bartelink
patent: 6075739 (2000-06-01), Ihara
patent: 6266722 (2001-07-01), Ogura
patent: 6548848 (2003-04-01), Horiguchi et al.
patent: 6720619 (2004-04-01), Chen et al.
patent: 7103522 (2006-09-01), Shepard
patent: 7352611 (2008-04-01), Isoda et al.
patent: 7397718 (2008-07-01), Bernstein et al.
patent: 2002/0038888 (2002-04-01), Kadowaki et al.
patent: 2002/0186572 (2002-12-01), Nishida et al.
patent: 2003/0078763 (2003-04-01), Chuang et al.
patent: 2005/0040881 (2005-02-01), Brown et al.
patent: 2005/0218942 (2005-10-01), Yamashita
patent: 2007/0198808 (2007-08-01), Bernstein et al.
patent: 2007/0242507 (2007-10-01), Bernstein et al.
patent: 2009/0109781 (2009-04-01), Bernstein et al.
patent: 2009/0287905 (2009-11-01), Bernstein et al.
Yang, Han, U.S. Appl. No. 12/180,776, Office Action, Mar. 22, 2010, 16 pages.
Yang, Han, U.S. Appl. No. 11/924,955, Notice of Allowance, May 5, 2010, 10 pages.
Yang, Han, U.S. Appl. No. 11/279,507, Office Action, Dec. 14, 2007, 30 pages.
Yang, Han, U.S. Appl. No. 11/279,507, Notice of Allowance, Jun. 30, 2008, 17 pages.
Yang, Han, U.S. Appl. No. 12/180,776, Notice of Allowance, Aug. 4, 2009, 9 pages.
Yang, Han, U.S. Appl. No. 12/180,776, Amendment to Office Action, 7 pages.
Yang, Han, U.S. Appl. No. 12/180,776, Office Action, Mar. 19, 2009, 9 pages.
Luu, Pho M., U.S. Appl. No. 12/045,744, Office Action, Jun. 9, 2010, 13 pages.
Luu, Pho M., U.S. Appl. No. 11/279,639, Notice of Allowance, Dec. 17, 2007, 12 pages.
Doan, Nghia M., U.S. Appl. No. 11/924,935, Office Action, Feb. 18, 2010, 10 pages.
Doan, Nghia M., U.S. Appl. No. 11/924,935, Notice of Allowance, Jun. 18, 2010, 8 pages.
Bernstein Kerry
Goodnow Kenneth J.
Ogilvie Clarence R.
Reynolds Christopher B.
Ventrone Sebastian T.
Cain David A.
Hoffman Warnick LLC
International Business Machines - Corporation
Pan Daniel
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