Processor path emulation system providing fast readout and verif

Details Processor path emulation system providing fast readout and verif Processor path emulation system providing fast readout and verif

1996-01-05

1998-12-15

Le, Dieu-Minh

Excavating

39518203, 39518507, 395308, 371 211, G06F 1100, G06F 1316

Patent

active

058505130

ABSTRACT:
A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

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