Processor nucleus combined with nucleus time controlled external

Details Processor nucleus combined with nucleus time controlled external Processor nucleus combined with nucleus time controlled external

1975-07-16

1977-06-14

Chapnick, Melvin B.

Communications: electrical

Digital comparator systems

G06F 300, G06F 738, G06F 912

Patent

active

040300765

ABSTRACT:
Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.

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patent: 3573741 (1971-04-01), Gavril
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patent: 3643223 (1972-02-01), Ruth et al.
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patent: 3710328 (1973-01-01), Hunter et al.
patent: 3805245 (1974-04-01), Brooks et al.
patent: 3916383 (1975-10-01), Malcolm
patent: 3936803 (1976-02-01), Katzman et al.

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