Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-02-04
2001-10-23
Kim, Kenneth S. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S020000, C712S200000
Reexamination Certificate
active
06308252
ABSTRACT:
TECHNICAL FIELD
The present invention relates to microprocessors and, in particular, to a microprocessor that has at least one standard datapath for single instruction stream, single data stream (SISD) instructions, but an enhanced datapath for single instruction, multiple data streams (SIMD) instructions.
BACKGROUND
In 1972, Flynn classified processors based on the flow of instructions and data. See Flynn, M. J., “Some Computer Organizations and Their Effectiveness”, IEEE Trans. Comput., C-21, 1972, 948-960. The four basis classes of processors are:
SISD, for Single Instruction, Single Data
SIMD, for Single Instruction, Multiple Data
MIMD, for Multiple Instruction, Multiple Data
MISD, for Multiple Instruction, Single Data.
The present patent application deals with SISD and MIMD.
Briefly, simple scalar machines appear as SISD computers. That is, SISD computers have both single instruction and data streams. While SIMD computers also have a single instruction stream, decoded in a single command decoder unit, SIMD computers have multiple data streams.
One early example of a SIMD microprocessor is the Intel i860, a 32-bit reduced instruction set computer (RISC) processor that allows each of its 32-bit general register to be viewed as a concatenation of separate smaller-width data quantities (e.g., four 8-bit data quantities), with no connection between those smaller-width data quantities. The i860 is actually a hybrid SISD/SIMD machine. Specifically, the i860 can operate on 32-bit data quantities in response to a single instruction (single instruction, single data, or SISD); or the i860 can operate on four 8-bit data quantities in parallel, also in response to a single instruction (thus the name single instruction, multiple data, or SIMD). Significantly, the i860 32-bit (maximum) SISD data path is of equal size to the 32-bit (maximum) SIMD data path. Similarly, other SISD/SIMD machines, such as the Sun SPARC (from Sun Microsystems, of Mountain View, Calif.), the DEC Alpha (from Compaq Computer Corporation of Dallas, Tex.) and the HP Precision Architecture (from Hewlett Packard Company of Palo Alto, Calif.) are also configured such that the SIMD data path is of equal size to the maximum SISD data path.
A disadvantage of this approach (the SIMD data path being of equal size to the SISD data path) is that the maximum size of the SIMD data path is limited by the size of the SISD data path, thus correspondingly limiting the amount of multiple data items (or, more correctly, the aggregate size of the multiple data items) that can be operated upon in response to a single instruction. That is, taking the example of the i860, the 32-bit size of the SIMD data path is limited to the 32-bit size of the non-SIMD data path.
SUMMARY
A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry sequentially decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit maximum) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m<n for any m. In addition, the AL circuitry is operable to perform multiple parallel operations on at least two portions of the one n-bit operand provided from the n-bit register circuitry. The multiple parallel operations are performed responsive to a second single instruction decoded by the instruction decode circuitry.
REFERENCES:
patent: 5150290 (1992-09-01), Hunt
patent: 5852726 (1998-12-01), Liu et al.
patent: 6122725 (2000-09-01), Roussel et al.
M.J. Flynn, “Some Computer Organizations and their Effectiveness”, IEEE Tran. Comput., C-21, 1972, 948-960.
Agarwal Rakesh
Malik Kamran
Teruyama Tatsuo
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Kim Kenneth S.
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