Information security – Access control or authentication – Network
Reexamination Certificate
2006-08-24
2011-11-15
Arani, Taghi (Department: 2438)
Information security
Access control or authentication
Network
C713S168000, C713S169000, C713S170000, C713S171000, C713S172000, C713S173000, C713S174000, C713S182000, C713S183000, C713S184000, C713S185000, C713S186000, C726S002000, C726S003000, C726S004000, C726S005000, C726S006000, C726S007000, C726S008000, C709S225000, C709S229000
Reexamination Certificate
active
08060925
ABSTRACT:
A processor communicating with a first memory configured to store first information and first data, and communicating with a second memory configured to store second information and second data, includes a computing unit configured to perform computation using the first data and the second data; an storing unit configured integrally with the computing unit to store first authentication information and second authentication information; a reading unit configured to read out the first information and the second information; an authenticating unit configured to authenticate the first memory by comparing the first information and the first authentication information, and to authenticate the second memory by comparing the second information and the second authentication information; and an controlling unit configured to control an access of the computing unit to the first memory and the second memory based on a result of the authentications.
REFERENCES:
patent: 5179517 (1993-01-01), Sarbin et al.
patent: 5237609 (1993-08-01), Kimura
patent: 6240517 (2001-05-01), Nishioka
patent: 2002/0064074 (2002-05-01), Kamise et al.
patent: 2003/0056107 (2003-03-01), Cammack et al.
patent: 2003/0140234 (2003-07-01), Noda et al.
patent: 2005/0037736 (2005-02-01), Jung
patent: 6-332731 (1994-12-01), None
patent: 2001-325580 (2001-11-01), None
patent: 2002-25278 (2002-01-01), None
patent: 2002-236667 (2002-08-01), None
patent: 2003-108257 (2003-04-01), None
patent: 2005-65222 (2005-03-01), None
patent: 2005-157542 (2005-06-01), None
patent: WO 03/058412 (2003-07-01), None
patent: WO2005048111 (2005-05-01), None
Notice of Rejection issued by the Japanese Patent Office on Dec. 22, 2009, for Japanese Patent Application No. 2005-254048, and Partial English Translation thereof.
Notice of Rejection, dated Jun. 1, 2010, issued by the Japanese Patent Office in Japanese Patent Application No. 2005-254048 (6 pages).
Kanai, “Processor, Memory, Computer System, System LSI, and Method of Authentication”, U.S. Appl. No. 11/350,798, filed Feb. 10, 2006.
Kanai Tatsunori
Yoshii Kenichiro
Arani Taghi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Jeudy Josnel
Kabushiki Kaisha Toshiba
LandOfFree
Processor, memory, computer system, and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor, memory, computer system, and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor, memory, computer system, and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4264398