Processor interrupt system

Details Processor interrupt system Processor interrupt system

1978-07-31

1980-04-29

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 918

Patent

active

042009120

ABSTRACT:
A digital data processor having the capability of handling more than one interrupt wherein one of the interrupts is a fast interrupt is provided. Interrupts are received by a priority network which establishes the priority of the interrupts should more than one interrupt occur at the same time. The output of the priority network is stored in a latch and the output of the latch is coupled to a vector and code logic circuit which encodes the vector address for the interrupt received. Whenever a fast interrupt is received a flag is set in a storage means so that when the system returns from interrupt it will be able to determine whether a fast interrupt had been serviced or not.

REFERENCES:
patent: 4003028 (1977-01-01), Bennett et al.
patent: 4090238 (1978-05-01), Russo
patent: 4152761 (1979-05-01), Louie

Affiliated with

Also associated with

Rating

Processor interrupt system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor interrupt system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor interrupt system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1686319