Data processing: structural design – modeling – simulation – and em – Emulation – In-circuit emulator
Reexamination Certificate
2000-01-31
2003-09-02
Jones, Hugh (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
In-circuit emulator
C703S023000, C703S014000, C716S030000, C716S030000, C716S030000, C714S033000, C714S036000
Reexamination Certificate
active
06615167
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the testing of computer system designs by software simulation, and more particularly to a verification methodology for system-on-chip (SOC) designs which enables the substitution of different embedded processor models into a design for simulation to be accomplished efficiently.
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip”, or Soc.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design (for example, a core as describe above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores interconnected as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core; simulation which includes a processor core tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the design.
However, inefficiencies in current verification methodologies exacerbate time pressures. Typically, the embedded processor type is different for different SOC designs. However, processor-specific code for configuring the processor core used in a particular SOC design may be distributed throughout the overall verification code, and executed on an as-needed basis. Consequently, if the processor core for which this specific code was written is replaced in simulation by a different processor core, for instance, to test a new SOC design, errors can occur. Typically, a substantial effort in locating and re-writing the processor-specific portions of the overall verification code to adjust for a change in processor type is required, incurring additional time-to-market delays.
A verification methodology is needed which addresses the foregoing problem.
SUMMARY OF THE INVENTION
According to the method of the present invention, in verification software for verifying a SOC design including an embedded processor, processor-specific code for performing processor-specific operations is localized in a processor driver. In response to requests from the verification software, the processor driver performs processor initialization and other processor-specific operations related to a particular embedded processor to be used in a verification test.
The method allows the processor type in a verification test to be readily changed, since processor-specific operations are centralized in the processor driver rather than distributed throughout the overall verification code. As a result, changing the processor type entails only changing or replacing the processor driver, while the rest of the verification code requires no changing. Consequently, verification is more efficient and time-to-market is reduced.
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Devins Robert J.
Ferro Paul G.
Herzl Robert D.
Connolly Bove & Lodge & Hutz LLP
Ferris Fred
Hume Larry J.
International Business Machines - Corporation
Jones Hugh
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