Processor independent error checking arrangement

Details Processor independent error checking arrangement Processor independent error checking arrangement

1997-07-09

1998-06-09

Beausoliel, Jr., Robert W.

Excavating

39518208, G06F 1100

Patent

active

057646600

ABSTRACT:
A dual processor computer system with error checking that stops immediately when a discrepancy is detected between the two processors. The system includes a first processor for executing a series of instructions including input/output instructions. A second processor executes the same instructions independently of and in synchronization with the first processor. Both processors have a processor independent bus interface. All significant processor address, data, and control signals are connected to all peripheral devices by a processor independent I/O bus. A comparison circuit detects discrepancies in the operation of the two lock step processors and provides a signal that immediately stops operation of the processors when an error is detected. Each processor is connected through its associated processor independent bus interface to the comparison circuit and the first processor is also connected through its interface to the I/O bus. The I/O bus is independent of the processor type, clock rate, and peripherals chosen in the construction of the computing system. This independence allows the computing system to be upgraded with faster processors and newer peripherals, without having to redesign the error checking circuitry.

REFERENCES:
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patent: 4049957 (1977-09-01), Kera et al.
patent: 4251873 (1981-02-01), Joby
patent: 4456952 (1984-06-01), Mohrman et al.
patent: 4907228 (1990-03-01), Bruckert et al.
patent: 5136595 (1992-08-01), Kimura

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