Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1999-03-19
2001-11-27
Dam, Tuan Q. (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C714S038110, C714S034000
Reexamination Certificate
active
06324684
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of embedded processors, and more particularly to a processor having real-time execution control for debug functions without a debug monitor.
BACKGROUND OF THE INVENTION
Embedded processors are widely used in a variety of applications and generally include processor circuitry that executes embedded code to perform desired functions. One type of embedded processor is a microcontroller which can be used, for example, to control the operation of a device, such as a motor. Another type of embedded processor is a digital signal processor (DSP) which can be used, for example, in a variety of communications products, such as cellular phones. The use of an embedded processor to perform desired functions generally requires the development and debug of the embedded code. In many applications, the embedded code includes foreground code for performing time critical tasks and background code for performing administrative or higher level tasks.
For certain applications, it can be particularly important to be able to debug the embedded code using real-time execution control. It can also be important to provide for real-time debug access to registers and memory in an embedded processor without using a debug monitor and without stopping the processor. Real-time execution control allows for the suspension of the embedded processor's execution of a given task while still allowing the processor to continue to service other, time critical tasks. Thus, real-time execution control allows the user of processor development and debug tools to interactively control the execution of embedded code within the system without necessarily interfering with the processor's ability to perform time critical tasks. For example, if embedded code is being debugged in a processor used to control a hard disk drive motor, the processor should not be allowed to stop controlling that motor. Otherwise, the motor may go out of control and destroy the hard disk drive. Thus, it is important to allow the processor to continue to execute the time critical task of controlling the motor while the embedded instruction code is being debugged.
One conventional execution control method is to stop all processor execution upon a break event and not allow for any interrupts to be processed until execution resumes. This approach is taken in stop mode emulation schemes used in some processors. However, this does not allow for controlling the processor's execution in a real-time, embedded system.
Another conventional method is to have a break event trigger a special interrupt which causes the processor to execute an interrupt service routine in which the processor waits for either a command to resume execution or for an enabled, time critical interrupt to occur. This type of interrupt service routine is often referred to as a “debug monitor.” Thus, the debug monitor is implemented by code executed by the embedded processor after being placed in a debug state. This debug monitor approach provides a form of execution control and is used in some processors in addition to the use of stop mode emulation schemes.
In this debug monitor method, the special interrupt service routine typically communicates to a debug host through scanable registers. The debug host scans in commands and scans out results. When halted, the processor is actually inside the debug monitor, servicing time critical interrupt service routines while performing commands. Consequently, the debug monitor scheme suffers from problems in that it uses system resources such as program and data memory. In general, on chip memory is very expensive and possibly can be corrupted by the debug monitor. Further, performance overhead due to saving and restoring context is experienced as the debug monitor is entered and exited and time critical interrupts generally have to be blocked during this time period.
SUMMARY OF THE INVENTION
In accordance with the present invention, a processor having real-time execution control without a debug monitor is disclosed that provides advantages over prior processor debug schemes.
According to one aspect of the present invention, the processor includes processor circuitry operable to execute embedded code where the embedded code includes background code and foreground code. The processor also includes debug circuitry interfacing with the processor circuitry and operable to communicate with a debug host. The debug circuitry is operable to receive a debug halt command from the debug host. After receipt of the debug halt command, the processor circuitry is operable to suspend execution of the embedded code to allow debug of the embedded code. The processor circuitry is further operable, while execution of the embedded code is suspended, to respond to an enabled interrupt by executing foreground code associated with the enabled interrupt. In one embodiment, the debug circuitry has a run state machine indicating execution control directives by the debug host, and the processor circuitry has an execution state machine indicating execution of instructions by the processor circuitry.
A technical advantage of the present invention is the implementation of debug functions using debug circuitry built into an embedded processor. The debug functions can allow the processor to be halted in a manner similar to an idle instruction. Normal execution is then suspended, and the processor waits either for a run command sent from a debug host or for an interrupt that is enabled and designated as time critical. After performing any time critical interrupt service routine, the processor can return back to the suspended state.
Another technical advantage is the ability to handle a case where, with multiple sections of time critical code, one section of time critical code can be executed while another is stopped and debugged.
A further technical advantage of the present invention is that it allows for debug of a processor without requiring the code and performance overhead of a debug monitor. This reduces the cost of the processor by eliminating the need for the debug monitor code which typically would consume on-chip memory and add to the overall cost of the processor. Also, there is no need to consume processor resources (e.g., registers, stack space, or memory) to hold state data during the execution of a debug monitor.
Another technical advantage is that there is no relatively lengthy delay between a break event and an ability to service time critical interrupts due to setup time as occurs with a debug monitor.
Additionally, the present invention allows for the mimicking of a stop mode emulation scheme by indicating that no interrupts (enabled or not) are time critical. This essentially treats stop mode emulation as a subset of real-time emulation.
Further technical advantages of the present invention should be apparent from the drawings, description and claims.
REFERENCES:
patent: 4631361 (1986-12-01), Miller
patent: 5140671 (1992-08-01), Hayes et al.
patent: 5394544 (1995-02-01), Motoyama et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5689684 (1997-11-01), Mulchandani et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5828824 (1998-10-01), Swoboda
patent: 5943498 (1999-08-01), Yano et al.
patent: 5978902 (1999-11-01), Mann
patent: 6055619 (2000-04-01), North et al.
patent: 6070218 (2000-05-01), Giles et al.
patent: 6079032 (2000-06-01), Peri
patent: 6081783 (2000-06-01), Divine et al.
patent: 6081885 (2000-06-01), Deao et al.
patent: 6094729 (2000-07-01), Mann
patent: 6145123 (2000-11-01), Torrey et al.
patent: 6154856 (2000-11-01), Madduri et al.
patent: 6202104 (2001-03-01), Ober
patent: 6249907 (2001-06-01), Carter et al.
patent: 6256777 (2001-07-01), Ackerman
patent: 6260150 (2001-07-01), Whilehelmus et al.
patent: 6286132 (2001-04-01), Tanaka et al.
Title Ddbx-LPP; A dynamic software tool for debugging asynchronous distributed algorithms on loosely coupled parallel processors, author: Gernandez et al, source J Syst Software, 1993.*
Next Generation B
Madathil Karthikeyan
Matt David R.
Swoboda Gary L.
Brady W. James
Dam Tuan Q.
Das Chameli Chaudhuri
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
LandOfFree
Processor having real-time execution control for debug... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor having real-time execution control for debug..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor having real-time execution control for debug... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2613565