Processor having multiple datapath instances

Details Processor having multiple datapath instances Processor having multiple datapath instances

1997-12-16

2000-03-28

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

G06F 1500

Patent

active

060444487

ABSTRACT:
A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate datapath. The total processor datapath is the sum of the number of slices multiplied by the width of a slice. Accordingly, all general purpose registers in the processor are as wide as the total datapath. A program executing on the processor can determine the maximum number of slices available in a particular processor by reading a register. In addition, a program can select the number of slices it will use by writing to a different register. The processor replicates control signals for each active slice in the processor and supports instructions for transferring data among the slices. Furthermore, the processor supports a set of instructions for fetching and storing data between multiple slices and the memory. The effective addresses of the fetch and store instructions can either be aligned or misaligned with respect to slice boundaries and doubleword boundaries in the memory.

REFERENCES:
patent: 5333280 (1994-07-01), Ishikawa et al.
Alexandridis, "Bit-Sliced Microprocessor Architecture," IEEE, pp. 69-92, 1978.
Hayes, Computer Architecture and Organization, McGraw Hill, pp. 259-265, 1988.
PowerPC 603, RISC Microprocessor User's Manual, pp. 3-17 to 3-18, 1994.

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