Processor having decoder for decoding unmodified instruction set

Details Processor having decoder for decoding unmodified instruction set Processor having decoder for decoding unmodified instruction set

1993-08-10

1994-07-05

Lee, Thomas C.

Boots, shoes, and leggings

395375, 395425, 364247, 3642473, 3642474, 3642445, 3649765, 364933, 3649333, 36493361, 3649657, 364DIG2, G06F 9315, G06F 9312, G06F 930

Patent

active

053275713

ABSTRACT:
A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

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