Processor having auxiliary operand register file and complementa

Details Processor having auxiliary operand register file and complementa Processor having auxiliary operand register file and complementa

1995-05-15

1999-10-12

Lee, Thomas C.

395393, 395591, 395733, G06F 1210

Patent

active

059665297

ABSTRACT:
A processor having a virtually addressable primary operand register file (PORF) is further provided with an auxiliary operand register file (AORF) to facilitate non-disruptive adjunct Execution. Preferably, the processor is further provided with basic and extended interrupt/exception (I/E) microcode as well as an AORF stack for recursively making available the AORF to the I/E service routines (ISR/ESR), utilizing the AORF stack, for nested servicing of I/E's. In some embodiments, the processor is further provided with micro-trap microcode, a first writable control store facility (WCSF), first auxiliary execution units (AEU) and multiple micro-trap service routines of a first and a second type comprising a number of uniterruptable series' of micro operations for performing complex tasks, leveraging the AORF and optionally the first AEU's. Lastly, in some embodiments, the processor is further/alternatively provided with macro-trap microcode, second WCSF, second AEU's and macro library routines of a first and a second type comprising a number of interruptable series' of operations for performing frequently performed tasks, leveraging the AORF and optionally the second AEU's. As a result, the processor is particularly suited for real-time/DSP systems.

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