Processor having an instruction set architecture implemented wit

Details Processor having an instruction set architecture implemented wit Processor having an instruction set architecture implemented wit

1997-11-03

1999-08-17

Pan, Daniel H.

39580042, 395595, G06F 922, G06F 938

Patent

active

059406267

ABSTRACT:
A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA. In one embodiment, primitive operations are statically organized into atomic units, which in turn are statically organized into snippets of execution threads. Selected ones of the snippets are logically associated together to form execution threads, which collectively implement the instructions of the ISA.

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Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 3, entitled "Instruction Set Design: Alternatives and Principles", pp. 89-137.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 5, entitled "Basic Processor Implementation Techniques", pp. 199-248.

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