Patent
1997-09-10
1999-09-07
Eng, David Y.
G06F 940
Patent
active
059499966
ABSTRACT:
A processor apparatus having a delayed branch execution function, for saving either the address at which the delayed branch instruction is stored when a completion type exception arises during the execution of a delayed branch instruction or the address at which the delayed branch instruction immediately before the delay slot instruction is stored when a cancellation type exception arises during the execution of a delay slot instruction, for retrieving the address at which the delayed branch instruction after executing an exception process handler is stored, and for reexecuting the delayed branch instruction. Another processor apparatus splits, during a pipeline process, an instruction fetch stage or a memory access stage during an instruction fetch or a memory access of operand data for an external memory, thereby enabling a simultaneous either operation for both inputting instruction data and outputting an address for a fetch of the succeeding instruction data or operation for both inputting operand data and outputting an address for an access of the succeeding operand data.
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Eng David Y.
Fujitsu Limited
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