Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2003-06-11
2008-03-11
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
C712S221000, C714S756000, C708S492000
Reexamination Certificate
active
07343472
ABSTRACT:
A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational code, destination information, and source information. The instruction decoder is operably coupled to interpret the instruction to identify the arithmetic logic unit and/or the finite field arithmetic unit to perform the operational code of the corresponding instruction. The instruction decoder then identifies at least one destination location within the digital storage device based on the destination information contained within the corresponding instruction. The instruction decoder then identifies at least one source location within the digital storage device based on the source information of the corresponding instruction. When the finite field arithmetic unit is to perform the operational code, it performs a finite field arithmetic function upon data stored in the at least one source location in accordance with the operational code and provides the resultant to the destination location.
REFERENCES:
patent: 6175941 (2001-01-01), Poeppelman et al.
patent: 6725356 (2004-04-01), Hansen et al.
Efficient Semisystolic Architectures for Finite-Field Arithmetic by Jain, Song and Parhi.
Johnson Scott D.
Kim Won
Nickolls John R.
Porten Joshua
Broadcom Corporation
Ellis Richard L.
Garlick & Harrison & Markison
Johnson Brian P
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